mirror of
https://github.com/cemu-project/Cemu
synced 2024-09-20 03:11:36 +02:00
Vulkan: Update some code to use VK_KHR_synchronization2
This commit is contained in:
Exzap
parent
49c55a3f56
commit
8f1cd4f925
3 changed files with 140 additions and 145 deletions
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@ -468,6 +468,15 @@ VulkanRenderer::VulkanRenderer()
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void* deviceExtensionFeatures = nullptr;
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// enable VK_KHR_synchonization_2
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VkPhysicalDeviceSynchronization2FeaturesKHR sync2Feature{};
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{
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sync2Feature.sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR;
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sync2Feature.pNext = deviceExtensionFeatures;
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deviceExtensionFeatures = &sync2Feature;
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sync2Feature.synchronization2 = VK_TRUE;
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}
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// enable VK_EXT_pipeline_creation_cache_control
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VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT cacheControlFeature{};
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if (m_featureControl.deviceExtensions.pipeline_creation_cache_control)
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@ -2852,13 +2861,20 @@ void VulkanRenderer::DrawBackbufferQuad(LatteTextureView* texView, RendererOutpu
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ClearColorbuffer(padView);
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// barrier for input texture
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VkMemoryBarrier memoryBarrier{};
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memoryBarrier.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
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VkPipelineStageFlags srcStage = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | VK_PIPELINE_STAGE_TRANSFER_BIT;
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VkPipelineStageFlags dstStage = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
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memoryBarrier.srcAccessMask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_TRANSFER_WRITE_BIT;
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memoryBarrier.dstAccessMask = VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_SHADER_READ_BIT;
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vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStage, dstStage, 0, 1, &memoryBarrier, 0, nullptr, 0, nullptr);
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{
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VkMemoryBarrier2 memoryBarrier2{};
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memoryBarrier2.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2;
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memoryBarrier2.srcStageMask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR | VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR;
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memoryBarrier2.dstStageMask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR;
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memoryBarrier2.srcAccessMask = VK_ACCESS_2_MEMORY_WRITE_BIT;
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memoryBarrier2.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT;
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VkDependencyInfo dependencyInfo{};
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dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
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dependencyInfo.dependencyFlags = 0;
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dependencyInfo.memoryBarrierCount = 1;
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dependencyInfo.pMemoryBarriers = &memoryBarrier2;
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vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
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}
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auto pipeline = backbufferBlit_createGraphicsPipeline(m_swapchainDescriptorSetLayout, padView, shader);
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@ -728,201 +728,192 @@ private:
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IMAGE_READ = 0x20,
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IMAGE_WRITE = 0x40,
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};
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template<uint32 TSyncOp>
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void barrier_calcStageAndMask(VkPipelineStageFlags& stages, VkAccessFlags& accessFlags)
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void barrier_calcStageAndMask(VkPipelineStageFlags2& stages, VkAccessFlags2& accessFlags)
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{
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stages = 0;
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accessFlags = 0;
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if constexpr ((TSyncOp & BUFFER_SHADER_READ) != 0)
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{
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// in theory: VK_ACCESS_INDEX_READ_BIT should be set here too but indices are currently separated
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stages |= VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT | VK_ACCESS_UNIFORM_READ_BIT | VK_ACCESS_SHADER_READ_BIT;
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// in theory: VK_ACCESS_2_INDEX_READ_BIT should be set here too but indices are currently separated
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stages |= VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT | VK_ACCESS_2_UNIFORM_READ_BIT | VK_ACCESS_2_SHADER_READ_BIT;
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}
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if constexpr ((TSyncOp & BUFFER_SHADER_WRITE) != 0)
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{
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stages |= VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_SHADER_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_2_SHADER_WRITE_BIT;
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}
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if constexpr ((TSyncOp & ANY_TRANSFER) != 0)
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{
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//stages |= VK_PIPELINE_STAGE_TRANSFER_BIT | VK_PIPELINE_STAGE_HOST_BIT;
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//accessFlags |= VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT | VK_ACCESS_HOST_READ_BIT | VK_ACCESS_HOST_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT;
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//accessFlags |= VK_ACCESS_MEMORY_READ_BIT;
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//accessFlags |= VK_ACCESS_MEMORY_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_2_TRANSFER_READ_BIT | VK_ACCESS_2_TRANSFER_WRITE_BIT;
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}
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if constexpr ((TSyncOp & TRANSFER_READ) != 0)
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{
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stages |= VK_PIPELINE_STAGE_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_TRANSFER_READ_BIT;
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//accessFlags |= VK_ACCESS_MEMORY_READ_BIT;
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stages |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_2_TRANSFER_READ_BIT;
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}
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if constexpr ((TSyncOp & TRANSFER_WRITE) != 0)
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{
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stages |= VK_PIPELINE_STAGE_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_TRANSFER_WRITE_BIT;
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//accessFlags |= VK_ACCESS_MEMORY_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
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accessFlags |= VK_ACCESS_2_TRANSFER_WRITE_BIT;
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}
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if constexpr ((TSyncOp & HOST_WRITE) != 0)
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{
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stages |= VK_PIPELINE_STAGE_HOST_BIT;
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accessFlags |= VK_ACCESS_HOST_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_HOST_BIT;
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accessFlags |= VK_ACCESS_2_HOST_WRITE_BIT;
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}
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if constexpr ((TSyncOp & HOST_READ) != 0)
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{
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stages |= VK_PIPELINE_STAGE_HOST_BIT;
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accessFlags |= VK_ACCESS_HOST_READ_BIT;
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stages |= VK_PIPELINE_STAGE_2_HOST_BIT;
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accessFlags |= VK_ACCESS_2_HOST_READ_BIT;
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}
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if constexpr ((TSyncOp & IMAGE_READ) != 0)
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{
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stages |= VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_SHADER_READ_BIT;
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stages |= VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT;
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accessFlags |= VK_ACCESS_2_SHADER_READ_BIT;
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stages |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
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accessFlags |= VK_ACCESS_COLOR_ATTACHMENT_READ_BIT;
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stages |= VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
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accessFlags |= VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT;
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stages |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
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accessFlags |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT;
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stages |= VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT;
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accessFlags |= VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT;
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}
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if constexpr ((TSyncOp & IMAGE_WRITE) != 0)
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{
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stages |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
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accessFlags |= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
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accessFlags |= VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
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accessFlags |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
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stages |= VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT;
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accessFlags |= VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
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}
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}
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template<uint32 TSrcSyncOp, uint32 TDstSyncOp>
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void barrier_bufferRange(VkBuffer buffer, VkDeviceSize offset, VkDeviceSize size)
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{
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VkBufferMemoryBarrier bufMemBarrier{};
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bufMemBarrier.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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VkBufferMemoryBarrier2 bufMemBarrier{};
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bufMemBarrier.sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2;
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bufMemBarrier.pNext = nullptr;
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bufMemBarrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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VkPipelineStageFlags srcStages = 0;
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VkPipelineStageFlags dstStages = 0;
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bufMemBarrier.srcAccessMask = 0;
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bufMemBarrier.dstAccessMask = 0;
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barrier_calcStageAndMask<TSrcSyncOp>(srcStages, bufMemBarrier.srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOp>(dstStages, bufMemBarrier.dstAccessMask);
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barrier_calcStageAndMask<TSrcSyncOp>(bufMemBarrier.srcStageMask, bufMemBarrier.srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOp>(bufMemBarrier.dstStageMask, bufMemBarrier.dstAccessMask);
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bufMemBarrier.buffer = buffer;
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bufMemBarrier.offset = offset;
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bufMemBarrier.size = size;
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vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStages, dstStages, 0, 0, nullptr, 1, &bufMemBarrier, 0, nullptr);
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VkDependencyInfo depInfo{};
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depInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
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depInfo.pNext = nullptr;
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depInfo.bufferMemoryBarrierCount = 1;
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depInfo.pBufferMemoryBarriers = &bufMemBarrier;
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vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &depInfo);
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}
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template<uint32 TSrcSyncOpA, uint32 TDstSyncOpA, uint32 TSrcSyncOpB, uint32 TDstSyncOpB>
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void barrier_bufferRange(VkBuffer bufferA, VkDeviceSize offsetA, VkDeviceSize sizeA,
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VkBuffer bufferB, VkDeviceSize offsetB, VkDeviceSize sizeB)
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{
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VkPipelineStageFlags srcStagesA = 0;
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VkPipelineStageFlags dstStagesA = 0;
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VkPipelineStageFlags srcStagesB = 0;
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VkPipelineStageFlags dstStagesB = 0;
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VkBufferMemoryBarrier2 bufMemBarrier2[2] = {};
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bufMemBarrier2[0].sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2_KHR;
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bufMemBarrier2[0].pNext = nullptr;
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bufMemBarrier2[0].srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier2[0].dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier2[0].buffer = bufferA;
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bufMemBarrier2[0].offset = offsetA;
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bufMemBarrier2[0].size = sizeA;
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barrier_calcStageAndMask<TSrcSyncOpA>(bufMemBarrier2[0].srcStageMask, bufMemBarrier2[0].srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOpA>(bufMemBarrier2[0].dstStageMask, bufMemBarrier2[0].dstAccessMask);
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VkBufferMemoryBarrier bufMemBarrier[2];
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bufMemBarrier2[1].sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER_2_KHR;
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bufMemBarrier2[1].pNext = nullptr;
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bufMemBarrier2[1].srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier2[1].dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier2[1].buffer = bufferB;
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bufMemBarrier2[1].offset = offsetB;
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bufMemBarrier2[1].size = sizeB;
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barrier_calcStageAndMask<TSrcSyncOpB>(bufMemBarrier2[1].srcStageMask, bufMemBarrier2[1].srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOpB>(bufMemBarrier2[1].dstStageMask, bufMemBarrier2[1].dstAccessMask);
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bufMemBarrier[0].sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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bufMemBarrier[0].pNext = nullptr;
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bufMemBarrier[0].srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier[0].dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier[0].srcAccessMask = 0;
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bufMemBarrier[0].dstAccessMask = 0;
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barrier_calcStageAndMask<TSrcSyncOpA>(srcStagesA, bufMemBarrier[0].srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOpA>(dstStagesA, bufMemBarrier[0].dstAccessMask);
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bufMemBarrier[0].buffer = bufferA;
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bufMemBarrier[0].offset = offsetA;
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bufMemBarrier[0].size = sizeA;
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bufMemBarrier[1].sType = VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER;
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bufMemBarrier[1].pNext = nullptr;
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bufMemBarrier[1].srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier[1].dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
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bufMemBarrier[1].srcAccessMask = 0;
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bufMemBarrier[1].dstAccessMask = 0;
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barrier_calcStageAndMask<TSrcSyncOpB>(srcStagesB, bufMemBarrier[1].srcAccessMask);
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barrier_calcStageAndMask<TDstSyncOpB>(dstStagesB, bufMemBarrier[1].dstAccessMask);
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bufMemBarrier[1].buffer = bufferB;
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bufMemBarrier[1].offset = offsetB;
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bufMemBarrier[1].size = sizeB;
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vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStagesA|srcStagesB, dstStagesA|dstStagesB, 0, 0, nullptr, 2, bufMemBarrier, 0, nullptr);
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VkDependencyInfo dependencyInfo = {};
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dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
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dependencyInfo.pNext = nullptr;
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dependencyInfo.bufferMemoryBarrierCount = 2;
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dependencyInfo.pBufferMemoryBarriers = bufMemBarrier2;
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vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
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}
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void barrier_sequentializeTransfer()
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{
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VkMemoryBarrier memBarrier{};
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memBarrier.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
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memBarrier.pNext = nullptr;
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VkMemoryBarrier2 memoryBarrier2{};
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memoryBarrier2.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2;
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memoryBarrier2.pNext = nullptr;
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memoryBarrier2.srcStageMask = VK_PIPELINE_STAGE_2_TRANSFER_BIT;
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memoryBarrier2.srcAccessMask = VK_ACCESS_2_TRANSFER_READ_BIT | VK_ACCESS_2_TRANSFER_WRITE_BIT;
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memoryBarrier2.dstStageMask = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT;
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memoryBarrier2.dstAccessMask = VK_ACCESS_2_MEMORY_READ_BIT | VK_ACCESS_2_MEMORY_WRITE_BIT;
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VkPipelineStageFlags srcStages = VK_PIPELINE_STAGE_TRANSFER_BIT;
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VkPipelineStageFlags dstStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
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memBarrier.srcAccessMask = VK_ACCESS_TRANSFER_READ_BIT | VK_ACCESS_TRANSFER_WRITE_BIT;
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memBarrier.dstAccessMask = 0;
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memBarrier.srcAccessMask |= (VK_ACCESS_MEMORY_READ_BIT | VK_ACCESS_MEMORY_WRITE_BIT);
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memBarrier.dstAccessMask |= (VK_ACCESS_MEMORY_READ_BIT | VK_ACCESS_MEMORY_WRITE_BIT);
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vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStages, dstStages, 0, 1, &memBarrier, 0, nullptr, 0, nullptr);
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VkDependencyInfo dependencyInfo{};
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dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
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dependencyInfo.pNext = nullptr;
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dependencyInfo.memoryBarrierCount = 1;
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dependencyInfo.pMemoryBarriers = &memoryBarrier2;
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dependencyInfo.bufferMemoryBarrierCount = 0;
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dependencyInfo.imageMemoryBarrierCount = 0;
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vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
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}
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void barrier_sequentializeCommand()
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{
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VkPipelineStageFlags srcStages = VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT;
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VkPipelineStageFlags dstStages = VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
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VkMemoryBarrier2 memoryBarrier = {};
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memoryBarrier.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2;
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memoryBarrier.srcStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR;
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memoryBarrier.srcAccessMask = 0;
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memoryBarrier.dstStageMask = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR;
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memoryBarrier.dstAccessMask = 0;
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vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStages, dstStages, 0, 0, nullptr, 0, nullptr, 0, nullptr);
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VkDependencyInfo dependencyInfo = {};
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dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
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dependencyInfo.dependencyFlags = 0;
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dependencyInfo.memoryBarrierCount = 1;
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dependencyInfo.pMemoryBarriers = &memoryBarrier;
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vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
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}
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template<uint32 TSrcSyncOp, uint32 TDstSyncOp>
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void barrier_image(VkImage imageVk, VkImageSubresourceRange& subresourceRange, VkImageLayout oldLayout, VkImageLayout newLayout)
|
||||
{
|
||||
VkPipelineStageFlags srcStages = 0;
|
||||
VkPipelineStageFlags dstStages = 0;
|
||||
VkImageMemoryBarrier2 imageMemBarrier2{};
|
||||
imageMemBarrier2.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2;
|
||||
imageMemBarrier2.oldLayout = oldLayout;
|
||||
imageMemBarrier2.newLayout = newLayout;
|
||||
imageMemBarrier2.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
|
||||
imageMemBarrier2.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
|
||||
imageMemBarrier2.image = imageVk;
|
||||
imageMemBarrier2.subresourceRange = subresourceRange;
|
||||
|
||||
VkImageMemoryBarrier imageMemBarrier{};
|
||||
imageMemBarrier.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER;
|
||||
imageMemBarrier.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
|
||||
imageMemBarrier.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED;
|
||||
imageMemBarrier.srcAccessMask = 0;
|
||||
imageMemBarrier.dstAccessMask = 0;
|
||||
barrier_calcStageAndMask<TSrcSyncOp>(srcStages, imageMemBarrier.srcAccessMask);
|
||||
barrier_calcStageAndMask<TDstSyncOp>(dstStages, imageMemBarrier.dstAccessMask);
|
||||
imageMemBarrier.image = imageVk;
|
||||
imageMemBarrier.subresourceRange = subresourceRange;
|
||||
imageMemBarrier.oldLayout = oldLayout;
|
||||
imageMemBarrier.newLayout = newLayout;
|
||||
barrier_calcStageAndMask<TSrcSyncOp>(imageMemBarrier2.srcStageMask, imageMemBarrier2.srcAccessMask);
|
||||
barrier_calcStageAndMask<TDstSyncOp>(imageMemBarrier2.dstStageMask, imageMemBarrier2.dstAccessMask);
|
||||
|
||||
vkCmdPipelineBarrier(m_state.currentCommandBuffer,
|
||||
srcStages, dstStages,
|
||||
0,
|
||||
0, NULL,
|
||||
0, NULL,
|
||||
1, &imageMemBarrier);
|
||||
VkDependencyInfo dependencyInfo{};
|
||||
dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO;
|
||||
dependencyInfo.imageMemoryBarrierCount = 1;
|
||||
dependencyInfo.pImageMemoryBarriers = &imageMemBarrier2;
|
||||
vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
|
||||
}
|
||||
|
||||
template<uint32 TSrcSyncOp, uint32 TDstSyncOp>
|
||||
|
|
@ -942,7 +933,6 @@ private:
|
|||
vkTexture->SetImageLayout(subresourceRange, newLayout);
|
||||
}
|
||||
|
||||
|
||||
public:
|
||||
bool GetDisableMultithreadedCompilation() const { return m_featureControl.disableMultithreadedCompilation; }
|
||||
bool UseTFViaSSBO() const { return m_featureControl.mode.useTFEmulationViaSSBO; }
|
||||
|
|
|
|||
|
|
@ -1033,29 +1033,18 @@ void VulkanRenderer::sync_inputTexturesChanged()
|
|||
// barrier here
|
||||
if (writeFlushRequired)
|
||||
{
|
||||
VkMemoryBarrier memoryBarrier{};
|
||||
memoryBarrier.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER;
|
||||
memoryBarrier.srcAccessMask = 0;
|
||||
memoryBarrier.dstAccessMask = 0;
|
||||
|
||||
VkPipelineStageFlags srcStage = 0;
|
||||
VkPipelineStageFlags dstStage = 0;
|
||||
|
||||
// src
|
||||
srcStage |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
|
||||
memoryBarrier.srcAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
|
||||
|
||||
srcStage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT;
|
||||
memoryBarrier.srcAccessMask |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
|
||||
|
||||
// dst
|
||||
dstStage |= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
|
||||
memoryBarrier.dstAccessMask |= VK_ACCESS_COLOR_ATTACHMENT_READ_BIT | VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_SHADER_READ_BIT;
|
||||
|
||||
dstStage |= VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT;
|
||||
memoryBarrier.dstAccessMask |= VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT | VK_ACCESS_SHADER_READ_BIT;
|
||||
|
||||
vkCmdPipelineBarrier(m_state.currentCommandBuffer, srcStage, dstStage, 0, 1, &memoryBarrier, 0, nullptr, 0, nullptr);
|
||||
VkMemoryBarrier2 memoryBarrier2{};
|
||||
memoryBarrier2.sType = VK_STRUCTURE_TYPE_MEMORY_BARRIER_2_KHR;
|
||||
memoryBarrier2.srcStageMask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR | VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR;
|
||||
memoryBarrier2.srcAccessMask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR;
|
||||
memoryBarrier2.dstStageMask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR | VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR;
|
||||
memoryBarrier2.dstAccessMask = VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR | VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR | VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR | VK_ACCESS_2_SHADER_READ_BIT_KHR;
|
||||
VkDependencyInfo dependencyInfo{};
|
||||
dependencyInfo.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO_KHR;
|
||||
dependencyInfo.dependencyFlags = 0;
|
||||
dependencyInfo.memoryBarrierCount = 1;
|
||||
dependencyInfo.pMemoryBarriers = &memoryBarrier2;
|
||||
vkCmdPipelineBarrier2KHR(m_state.currentCommandBuffer, &dependencyInfo);
|
||||
|
||||
performanceMonitor.vk.numDrawBarriersPerFrame.increment();
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue