mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-09-20 03:11:51 +02:00
DSP: I hereby name R08-R11 WR0-WR3, standing for Wrap control Registers 0-3.
Kill "CR". Document decrements a little bit. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3126 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
hrydgard
parent
9b642fa1f8
commit
0d57b7f01a
8 changed files with 95 additions and 114 deletions
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@ -457,6 +457,7 @@ void lri(const UDSPInstruction& opc)
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u8 reg = opc.hex & DSP_REG_MASK;
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u16 imm = dsp_fetch_code();
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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}
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// LRIS $(0x18+D), #I
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@ -468,6 +469,7 @@ void lris(const UDSPInstruction& opc)
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u8 reg = ((opc.hex >> 8) & 0x7) + DSP_REG_AXL0;
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u16 imm = (s8)opc.hex;
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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}
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// LR $D, @M
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@ -481,6 +483,7 @@ void lr(const UDSPInstruction& opc)
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u16 addr = dsp_fetch_code();
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u16 val = dsp_dmem_read(addr);
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dsp_op_write_reg(reg, val);
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dsp_conditional_extend_accum(reg);
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}
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// SR @M, $S
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@ -1392,12 +1395,7 @@ void dar(const UDSPInstruction& opc)
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{
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int reg = opc.hex & 0x3;
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int temp = g_dsp.r[reg] + g_dsp.r[DSP_REG_R08];
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if (temp <= 0x7ff) // ???
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g_dsp.r[reg] = temp;
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else
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g_dsp.r[reg]--;
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g_dsp.r[reg]--; // TODO: Wrap properly.
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}
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@ -1410,12 +1408,7 @@ void iar(const UDSPInstruction& opc)
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{
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int reg = opc.hex & 0x3;
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int temp = g_dsp.r[reg] + g_dsp.r[DSP_REG_R08];
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if (temp <= 0x7ff) // ???
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g_dsp.r[reg] = temp;
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else
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g_dsp.r[reg]++;
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g_dsp.r[reg]++; // TODO: Wrap properly according to the corresponding WR register.
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}
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//-------------------------------------------------------------
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@ -1476,7 +1469,7 @@ void srbith(const UDSPInstruction& opc)
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g_dsp.r[DSP_REG_SR] |= SR_TOP_BIT_UNK;
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break;
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// 40-bit precision? clamping? no idea :(
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// Automatic 40-bit sign extension when loading ACx.M.
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// 40 seems to be the default.
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// Confirmed these by using DSPSpy and copying the value of SR to R00 after setting.
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case 0xe: // SET16 (really, clear SR's 0x4000)
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@ -1583,7 +1576,7 @@ void mulmvz(const UDSPInstruction& opc)
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dsp_set_long_acc(rreg, acc);
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// math prod
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prod = (s64)g_dsp.r[DSP_REG_AXL0 + sreg] * (s64)g_dsp.r[DSP_REG_AXH0 + sreg] * GetMultiplyModifier();
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prod = (s64)(s16)g_dsp.r[DSP_REG_AXL0 + sreg] * (s64)(s16)g_dsp.r[DSP_REG_AXH0 + sreg] * GetMultiplyModifier();
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dsp_set_long_prod(prod);
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Update_SR_Register64(prod);
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@ -309,7 +309,6 @@ const DSPOPCTemplate cw =
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const DSPOPCTemplate opcodes_ext[] =
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{
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// FIXME: guessing this is cr need checking
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{"CR", 0x0000, 0x00fc, DSPInterpreter::Ext::cr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"DR", 0x0004, 0x00fc, DSPInterpreter::Ext::dr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"IR", 0x0008, 0x00fc, DSPInterpreter::Ext::ir, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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{"NR", 0x000c, 0x00fc, DSPInterpreter::Ext::nr, nop, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, NULL, NULL,},
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@ -401,14 +400,14 @@ const pdlabel_t regnames[] =
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{0x01, "AR1", "Addr Reg 01",},
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{0x02, "AR2", "Addr Reg 02",},
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{0x03, "AR3", "Addr Reg 03",},
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{0x04, "IX0", "Index Reg 0(04)",},
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{0x05, "IX1", "Index Reg 1(05)",},
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{0x06, "IX2", "Index Reg 2(06)",},
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{0x07, "IX3", "Indec Reg 3(07)",},
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{0x08, "R08", "Register 08",},
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{0x09, "R09", "Register 09",},
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{0x0a, "R10", "Register 10",},
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{0x0b, "R11", "Register 11",},
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{0x04, "IX0", "Index Reg 0",},
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{0x05, "IX1", "Index Reg 1",},
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{0x06, "IX2", "Index Reg 2",},
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{0x07, "IX3", "Index Reg 3",},
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{0x08, "WR0", "Wrapping Register 0",},
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{0x09, "WR1", "Wrapping Register 1",},
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{0x0a, "WR2", "Wrapping Register 2",},
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{0x0b, "WR3", "Wrapping Register 3",},
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{0x0c, "ST0", "Call stack",},
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{0x0d, "ST1", "Data stack",},
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{0x0e, "ST2", "Loop addr stack",},
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@ -435,6 +434,12 @@ const pdlabel_t regnames[] =
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{0x21, "ACC1", "Accu Full 1",},
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{0x22, "AX0", "Extra Accu 0",},
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{0x23, "AX1", "Extra Accu 1",},
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// Old names for the wrapping registers, for compatibility.
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{0x08, "R08", "Wrapping Register 0(08)",},
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{0x09, "R09", "Wrapping Register 1(09)",},
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{0x0a, "R10", "Wrapping Register 2(10)",},
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{0x0b, "R11", "Wrapping Register 3(11)",},
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};
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u8 opSize[OPTABLE_SIZE];
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@ -29,22 +29,21 @@
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// attached to opcodes that allow extending (8 lower bits of opcode not used by
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// opcode). Extended opcodes do not modify program counter $pc register.
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// Most of the suffixes increment or decrement one or more addressing registers
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// (the first four, ARx). The increment/decrement is either 1, or the corresponding
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// "index" register (the second four, IXx). The addressing registers will wrap
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// in odd ways, dictated by the corresponding wrapping register, WP0-3.
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// The following should be applied as a decrement:
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// ar[i] = (ar[i] & wp[i]) == 0 ? ar[i] | wp[i] : ar[i] - 1;
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// I have not found the corresponding algorithms for increments yet.
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// It's gotta be fairly simple though. See R3123, R3125 in Google Code.
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namespace DSPInterpreter
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{
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namespace Ext
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{
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// CR $arR
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// xxxx xxxx 0000 00rr
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// Clearing addressing register $arR.
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// This is not in any doc and as such just a guess
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void cr(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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g_dsp.r[reg] = 0;
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}
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// DR $arR
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// xxxx xxxx 0000 01rr
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// Decrement addressing register $arR.
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@ -208,7 +207,6 @@ void dsp_op_ext_r_epi(const UDSPInstruction& opc)
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{
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u8 op = (opc.hex >> 2) & 0x3;
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u8 reg = opc.hex & 0x3;
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switch (op) {
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case 0x00: //
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g_dsp.r[reg] = 0;
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@ -375,7 +373,6 @@ void dsp_op_ext_ld(const UDSPInstruction& opc)
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//
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//
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// ================================================================================
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void dsp_op_ext_ops_pro(const UDSPInstruction& opc)
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{
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if ((opc.hex & 0xFF) == 0){return;}
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@ -428,7 +425,10 @@ void dsp_op_ext_ops_pro(const UDSPInstruction& opc)
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void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
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{
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if ((opc.hex & 0xFF) == 0){return;}
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if ((opc.hex & 0xFF) == 0)
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{
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return;
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}
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switch ((opc.hex >> 4) & 0xf)
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{
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@ -436,7 +436,6 @@ void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
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case 0x09:
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case 0x0a:
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case 0x0b:
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if (opc.hex & 0x2)
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{
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dsp_op_ext_sl_epi(opc.hex);
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@ -450,5 +449,3 @@ void dsp_op_ext_ops_epi(const UDSPInstruction& opc)
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return;
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}
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}
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@ -62,7 +62,6 @@ void ldn(const UDSPInstruction& opc);
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void ldm(const UDSPInstruction& opc);
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void ldnm(const UDSPInstruction& opc);
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void mv(const UDSPInstruction& opc);
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void cr(const UDSPInstruction& opc);
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void dr(const UDSPInstruction& opc);
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void ir(const UDSPInstruction& opc);
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void nr(const UDSPInstruction& opc);
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@ -83,50 +83,19 @@ inline u16 dsp_op_read_reg(u8 reg)
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inline void dsp_op_write_reg(u8 reg, u16 val)
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{
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switch (reg & 0x1f) {
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/*
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case DSP_REG_ACH0:
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case DSP_REG_ACH1:
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// sign extend from the bottom 8 bits.
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g_dsp.r[reg] = (u16)(s16)(s8)(u8)val;
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break;
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*/
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case 0x0c:
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case 0x0d:
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case 0x0e:
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case 0x0f:
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dsp_reg_store_stack(reg - 0x0c, val);
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break;
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#if 0 // FIXME
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case 0x1e: // AC0.M
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case 0x1f: // AC1.M
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// in "s16 mode", LRI $AC0.M, xxx will set AC0.L and AC0.H to 0,
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// while it won't in "s40 mode".
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if (g_dsp.r[DSP_REG_SR] & SR_16_BIT) {
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g_dsp.r[reg - 0x2] = 0; // L
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g_dsp.r[reg - 0xe] = 0; // H
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}
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g_dsp.r[reg] = val;
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break;
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case 0x1c: // AC0.L
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case 0x1d: // AC1.L
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if (g_dsp.r[DSP_REG_SR] & SR_16_BIT) {
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g_dsp.r[reg + 0x2] = 0; // M
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g_dsp.r[reg - 0xc] = 0; // H
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}
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g_dsp.r[reg] = val;
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break;
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case 0x10: // AC0.H
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case 0x11: // AC1.H
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if (g_dsp.r[DSP_REG_SR] & SR_16_BIT) {
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g_dsp.r[reg + 0xc] = 0; // L
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g_dsp.r[reg + 0xe] = 0; // M
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}
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g_dsp.r[reg] = val;
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break;
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#endif
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default:
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g_dsp.r[reg] = val;
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@ -134,6 +103,25 @@ inline void dsp_op_write_reg(u8 reg, u16 val)
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}
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}
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inline void dsp_conditional_extend_accum(u8 reg)
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{
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#if 0
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switch (reg)
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{
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case DSP_REG_ACM0:
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case DSP_REG_ACM1:
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if (g_dsp.r[DSP_REG_SR] & SR_40_MODE_BIT)
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{
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// Sign extend into whole accum.
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u16 val = g_dsp.r[reg];
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g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACH0] = (val & 0x8000) ? 0xFFFF : 0x0000;
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g_dsp.r[reg - DSP_REG_ACM0 + DSP_REG_ACL0] = 0;
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}
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}
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#endif
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}
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// ---------------------------------------------------------------------------------------
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//
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@ -253,13 +241,13 @@ inline s64 dsp_get_long_acx(int _reg)
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inline s16 dsp_get_ax_l(int _reg)
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{
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_assert_(_reg < 2);
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return g_dsp.r[0x18 + _reg];
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return (s16)g_dsp.r[0x18 + _reg];
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}
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inline s16 dsp_get_ax_h(int _reg)
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{
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_assert_(_reg < 2);
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return g_dsp.r[0x1a + _reg];
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return (s16)g_dsp.r[0x1a + _reg];
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}
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#endif
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@ -31,19 +31,19 @@
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#define DSP_REG_AR0 0x00 // address registers
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#define DSP_REG_AR1 0x01
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#define DSP_REG_AR2 0x02
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#define DSP_REG_AR3 0x03 // used as jump function selector
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#define DSP_REG_AR3 0x03
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#define DSP_REG_IX0 0x04 // LEFT_VOLUME accel
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#define DSP_REG_IX1 0x05 // RIGHT_VOLUME accel
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#define DSP_REG_IX2 0x06 // ADDRH_SMP accel
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#define DSP_REG_IX3 0x07 // ADDRL_SMP accel
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#define DSP_REG_IX0 0x04 // indexing registers (actually, mostly used as increments)
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#define DSP_REG_IX1 0x05
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#define DSP_REG_IX2 0x06
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#define DSP_REG_IX3 0x07
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#define DSP_REG_R08 0x08 // fixed to 48000 value
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#define DSP_REG_R09 0x09 // problems using this
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#define DSP_REG_R0A 0x0a // ADDREH_SMP accel
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#define DSP_REG_R0B 0x0b // ADDREL_SMP accel
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#define DSP_REG_WR0 0x08 // address wrapping registers. should be initialized to 0xFFFF if not used.
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#define DSP_REG_WR1 0x09
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#define DSP_REG_WR2 0x0a
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#define DSP_REG_WR3 0x0b
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#define DSP_REG_ST0 0x0c
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#define DSP_REG_ST0 0x0c // stacks.
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#define DSP_REG_ST1 0x0d
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#define DSP_REG_ST2 0x0e
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#define DSP_REG_ST3 0x0f
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@ -51,15 +51,15 @@
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#define DSP_REG_CONFIG 0x12
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#define DSP_REG_SR 0x13
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#define DSP_REG_PRODL 0x14
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#define DSP_REG_PRODL 0x14 // product.
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#define DSP_REG_PRODM 0x15
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#define DSP_REG_PRODH 0x16
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#define DSP_REG_PRODM2 0x17
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#define DSP_REG_AXL0 0x18
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#define DSP_REG_AXL1 0x19
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#define DSP_REG_AXH0 0x1a // SMP_R accel
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#define DSP_REG_AXH1 0x1b // SMP_L accel
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#define DSP_REG_AXH0 0x1a
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#define DSP_REG_AXH1 0x1b
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#define DSP_REG_ACC0 0x1c // accumulator (global)
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#define DSP_REG_ACC1 0x1d
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@ -85,6 +85,7 @@
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#define DSP_REG_CMBH 0xfffe // CPU Mailbox H
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#define DSP_REG_CMBL 0xffff // CPU Mailbox L
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#define DMA_TO_DSP 0
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#define DMA_TO_CPU 1
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@ -92,7 +93,6 @@
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#define DSP_STACK_C 0
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#define DSP_STACK_D 1
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// SR bits
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#define SR_CARRY 0x0001
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#define SR_2 0x0002 // overflow???
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@ -107,7 +107,6 @@
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#define SR_40_MODE_BIT 0x4000 // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when loading mid accums.
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#define SR_TOP_BIT_UNK 0x8000 // 1 = normal. 0 = x2 (CLR15, SET15) ????????
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void dsp_reg_store_stack(u8 stack_reg, u16 val);
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u16 dsp_reg_load_stack(u8 stack_reg);
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@ -2,24 +2,24 @@
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incdir "tests"
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include "dsp_base.inc"
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; Tests done using AR1 = 0x0010, IX1 = 0. LP1 means R09.
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; LP1 = 0
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; Tests done using AR1 = 0x0010, IX1 = 0. WR1 (wrap 1) means R09.
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; WR1 = 0
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; 10, 10, 10, 10,
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; LP1 = 1
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; WR1 = 1
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; 10, 11, 10, 11,
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; LP1 = 2
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; WR1 = 2
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; 10, 12, 11, 13, 12, 11, 13, 12, 11, 13, 12, 11
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; LP1 = 3
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; WR1 = 3
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; 10, 13, 12, 11, 10, 13, 12...
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; LP1 = 4
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; WR1 = 4
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; 10, 14, 13, 17, 16, 15, 14, 13, 17, 16, 15, 14, 13, ...
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; LP1 = 5
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; WR1 = 5
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; 10, 15, 14, 13, 12, 17, 16, 15, 14, 13, 12, 17,
|
||||
; LP1 = 6
|
||||
; WR1 = 6
|
||||
; 10, 16, 15, 14, 13, 12, 11, 17, 16, 15, 14, 13
|
||||
; LP1 = 7
|
||||
; WR1 = 7
|
||||
; 10, 17, 16, 15, .. normal
|
||||
; LP1 = 8
|
||||
; WR1 = 8
|
||||
; 10, 18, 17, 1f, 1e, 1d, 1c, 1b, 1a, 19, 18, 17, 1f, 1e, .....
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -8,23 +8,23 @@ include "dsp_base.inc"
|
|||
; These were proven FALSE though by the following:
|
||||
|
||||
; Tests done using AR1 = 0x0010, IX1 = 0
|
||||
; LP1 = 0
|
||||
; WR1 = 0
|
||||
; 10, 11, 11, 11, 11......
|
||||
; LP1 = 1
|
||||
; WR1 = 1
|
||||
; 10, 11, 10, 11, 10......
|
||||
; LP1 = 2
|
||||
; WR1 = 2
|
||||
; 10, 11, 12, 13, 11, 12, 13, 11, 12, 13 ......
|
||||
; LP1 = 3
|
||||
; WR1 = 3
|
||||
; 10, 11, 12, 13, 10, 11, 12, 13, 10, 11, 12, 13.......
|
||||
; LP1 = 4
|
||||
; WR1 = 4
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 13, 14, 15, 16, 17, 13, 14, 15 ......
|
||||
; LP1 = 5
|
||||
; WR1 = 5
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 12, 13, 14, 15 ...
|
||||
; LP1 = 6
|
||||
; WR1 = 6
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 11, 12, 13, 14...
|
||||
; LP1 = 7
|
||||
; WR1 = 7
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 10, 11, ....
|
||||
; LP1 = 8
|
||||
; WR1 = 8
|
||||
; 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 1a, 1b, 1c, 1d, 1e, 1f, 17, 18, 19, 1a, 1b.....
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue