archive/dolphin
1
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2024-09-20 11:21:43 +02:00
Code Issues Projects Releases Packages Wiki Activity

PowerPC: Add PowerPCState parameter to UpdatePerformanceMonitor().

Browse source
This commit is contained in:
Admiral H. Curtiss 2023-01-10 02:22:23 +01:00
parent 61ba516570
commit 485bba238e
No known key found for this signature in database
GPG key ID: F051B4C4044F33FB
7 changed files with 29 additions and 24 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Source/Core/Core/CoreTiming.cpp
View file

@ -447,7 +447,7 @@ void CoreTimingManager::Idle()
system.GetFifo().FlushGpu(system);
}
PowerPC::UpdatePerformanceMonitor(PowerPC::ppcState.downcount, 0, 0);
PowerPC::UpdatePerformanceMonitor(PowerPC::ppcState.downcount, 0, 0, PowerPC::ppcState);
m_idled_cycles += DowncountToCycles(PowerPC::ppcState.downcount);
PowerPC::ppcState.downcount = 0;
}

6
Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
View file

@ -138,17 +138,17 @@ static void EndBlock(UGeckoInstruction data)
{
PowerPC::ppcState.pc = PowerPC::ppcState.npc;
PowerPC::ppcState.downcount -= data.hex;
PowerPC::UpdatePerformanceMonitor(data.hex, 0, 0);
PowerPC::UpdatePerformanceMonitor(data.hex, 0, 0, PowerPC::ppcState);
}
static void UpdateNumLoadStoreInstructions(UGeckoInstruction data)
{
PowerPC::UpdatePerformanceMonitor(0, data.hex, 0);
PowerPC::UpdatePerformanceMonitor(0, data.hex, 0, PowerPC::ppcState);
}
static void UpdateNumFloatingPointInstructions(UGeckoInstruction data)
{
PowerPC::UpdatePerformanceMonitor(0, 0, data.hex);
PowerPC::UpdatePerformanceMonitor(0, 0, data.hex, PowerPC::ppcState);
}
static void WritePC(UGeckoInstruction data)

2
Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
View file

@ -214,7 +214,7 @@ int Interpreter::SingleStepInner()
const GekkoOPInfo* opinfo = PPCTables::GetOpInfo(m_prev_inst);
PowerPC::UpdatePerformanceMonitor(opinfo->numCycles, (opinfo->flags & FL_LOADSTORE) != 0,
(opinfo->flags & FL_USE_FPU) != 0);
(opinfo->flags & FL_USE_FPU) != 0, PowerPC::ppcState);
return opinfo->numCycles;
}

4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View file

@ -538,8 +538,8 @@ bool Jit64::Cleanup()
if (MMCR0(PowerPC::ppcState).Hex || MMCR1(PowerPC::ppcState).Hex)
{
ABI_PushRegistersAndAdjustStack({}, 0);
ABI_CallFunctionCCC(PowerPC::UpdatePerformanceMonitor, js.downcountAmount, js.numLoadStoreInst,
js.numFloatingPointInst);
ABI_CallFunctionCCCP(PowerPC::UpdatePerformanceMonitor, js.downcountAmount, js.numLoadStoreInst,
js.numFloatingPointInst, &PowerPC::ppcState);
ABI_PopRegistersAndAdjustStack({}, 0);
did_something = true;
}

1
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View file

@ -294,6 +294,7 @@ void JitArm64::Cleanup()
MOVI2R(ARM64Reg::X0, js.downcountAmount);
MOVI2R(ARM64Reg::X1, js.numLoadStoreInst);
MOVI2R(ARM64Reg::X2, js.numFloatingPointInst);
MOVP2R(ARM64Reg::X3, &PowerPC::ppcState);
BLR(ARM64Reg::X8);
}
}

35
Source/Core/Core/PowerPC/PowerPC.cpp
View file

@ -403,63 +403,66 @@ void WriteFullTimeBaseValue(u64 value)
std::memcpy(&TL(PowerPC::ppcState), &value, sizeof(value));
}
void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst)
void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst,
PowerPCState& ppc_state)
{
switch (MMCR0(PowerPC::ppcState).PMC1SELECT)
switch (MMCR0(ppc_state).PMC1SELECT)
{
case 0: // No change
break;
case 1: // Processor cycles
PowerPC::ppcState.spr[SPR_PMC1] += cycles;
ppc_state.spr[SPR_PMC1] += cycles;
break;
default:
break;
}
switch (MMCR0(PowerPC::ppcState).PMC2SELECT)
switch (MMCR0(ppc_state).PMC2SELECT)
{
case 0: // No change
break;
case 1: // Processor cycles
PowerPC::ppcState.spr[SPR_PMC2] += cycles;
ppc_state.spr[SPR_PMC2] += cycles;
break;
case 11: // Number of loads and stores completed
PowerPC::ppcState.spr[SPR_PMC2] += num_load_stores;
ppc_state.spr[SPR_PMC2] += num_load_stores;
break;
default:
break;
}
switch (MMCR1(PowerPC::ppcState).PMC3SELECT)
switch (MMCR1(ppc_state).PMC3SELECT)
{
case 0: // No change
break;
case 1: // Processor cycles
PowerPC::ppcState.spr[SPR_PMC3] += cycles;
ppc_state.spr[SPR_PMC3] += cycles;
break;
case 11: // Number of FPU instructions completed
PowerPC::ppcState.spr[SPR_PMC3] += num_fp_inst;
ppc_state.spr[SPR_PMC3] += num_fp_inst;
break;
default:
break;
}
switch (MMCR1(PowerPC::ppcState).PMC4SELECT)
switch (MMCR1(ppc_state).PMC4SELECT)
{
case 0: // No change
break;
case 1: // Processor cycles
PowerPC::ppcState.spr[SPR_PMC4] += cycles;
ppc_state.spr[SPR_PMC4] += cycles;
break;
default:
break;
}
if ((MMCR0(PowerPC::ppcState).PMC1INTCONTROL && (PowerPC::ppcState.spr[SPR_PMC1] & 0x80000000) != 0) ||
(MMCR0(PowerPC::ppcState).PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC2] & 0x80000000) != 0) ||
(MMCR0(PowerPC::ppcState).PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC3] & 0x80000000) != 0) ||
(MMCR0(PowerPC::ppcState).PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC4] & 0x80000000) != 0))
PowerPC::ppcState.Exceptions |= EXCEPTION_PERFORMANCE_MONITOR;
if ((MMCR0(ppc_state).PMC1INTCONTROL && (ppc_state.spr[SPR_PMC1] & 0x80000000) != 0) ||
(MMCR0(ppc_state).PMCINTCONTROL && (ppc_state.spr[SPR_PMC2] & 0x80000000) != 0) ||
(MMCR0(ppc_state).PMCINTCONTROL && (ppc_state.spr[SPR_PMC3] & 0x80000000) != 0) ||
(MMCR0(ppc_state).PMCINTCONTROL && (ppc_state.spr[SPR_PMC4] & 0x80000000) != 0))
{
ppc_state.Exceptions |= EXCEPTION_PERFORMANCE_MONITOR;
}
}
void CheckExceptions()

3
Source/Core/Core/PowerPC/PowerPC.h
View file

@ -267,7 +267,8 @@ void RunLoop();
u64 ReadFullTimeBaseValue();
void WriteFullTimeBaseValue(u64 value);
void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst,
PowerPCState& ppc_state);
// Easy register access macros.
#define HID0(ppc_state) ((UReg_HID0&)(ppc_state).spr[SPR_HID0])