From 5f5b43c659ec0b4c0915c11d93c30b33ed01a41b Mon Sep 17 00:00:00 2001 From: nakeee Date: Mon, 6 Apr 2009 09:42:29 +0000 Subject: [PATCH] some docs small clean up fixed the loop size correctly I hope this time git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2893 8ced0084-cf51-0410-be5f-012b33b47a6e --- .../Src/DSPInterpreter.cpp | 158 +++++++++++++----- .../Src/DSPInterpreter.h | 6 + .../Plugin_DSP_LLE-testing/Src/DSPTables.cpp | 23 +-- 3 files changed, 137 insertions(+), 50 deletions(-) diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp index 74a7553e7f..9f2b6bcf02 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.cpp @@ -145,7 +145,8 @@ void loop(const UDSPInstruction& opc) g_dsp.pc = loop_pc; } - g_dsp.pc = loop_pc + opSize[dsp_peek_code()]; + // g_dsp.pc = loop_pc; + g_dsp.pc =+ opSize[dsp_peek_code()]; } void loopi(const UDSPInstruction& opc) @@ -159,7 +160,8 @@ void loopi(const UDSPInstruction& opc) g_dsp.pc = loop_pc; } - g_dsp.pc = loop_pc + opSize[dsp_peek_code()]; + // g_dsp.pc = loop_pc; + g_dsp.pc =+ opSize[dsp_peek_code()]; } void bloop(const UDSPInstruction& opc) @@ -176,7 +178,8 @@ void bloop(const UDSPInstruction& opc) } else { - g_dsp.pc = loop_pc + opSize[dsp_peek_code()]; + g_dsp.pc = loop_pc; + g_dsp.pc =+ opSize[dsp_peek_code()]; } } @@ -193,7 +196,8 @@ void bloopi(const UDSPInstruction& opc) } else { - g_dsp.pc = loop_pc + opSize[dsp_peek_code()]; + g_dsp.pc = loop_pc; + g_dsp.pc =+ opSize[dsp_peek_code()]; } } @@ -208,6 +212,10 @@ void mrr(const UDSPInstruction& opc) dsp_op_write_reg(dreg, val); } +// LRR $D, @$S +// 0001 1000 0ssd dddd +// Move value from data memory pointed by addressing register $S toregister $D. +// FIXME: Perform additional operation depending on destination register. void lrr(const UDSPInstruction& opc) { u8 sreg = (opc.hex >> 5) & 0x3; @@ -215,27 +223,59 @@ void lrr(const UDSPInstruction& opc) u16 val = dsp_dmem_read(g_dsp.r[sreg]); dsp_op_write_reg(dreg, val); - - // post processing of source reg - switch ((opc.hex >> 7) & 0x3) - { - case 0x0: // LRR - break; - - case 0x1: // LRRD - g_dsp.r[sreg]--; - break; - - case 0x2: // LRRI - g_dsp.r[sreg]++; - break; - - case 0x3: // LRRN - g_dsp.r[sreg] += g_dsp.r[sreg + 4]; - break; - } } +// LRRD $D, @$S +// 0001 1000 1ssd dddd +// Move value from data memory pointed by addressing register $S toregister $D. +// Decrement register $S. +// FIXME: Perform additional operation depending on destination register. +void lrrd(const UDSPInstruction& opc) +{ + u8 sreg = (opc.hex >> 5) & 0x3; + u8 dreg = opc.hex & 0x1f; + + u16 val = dsp_dmem_read(g_dsp.r[sreg]); + dsp_op_write_reg(dreg, val); + g_dsp.r[sreg]--; +} + +// LRRI $D, @$S +// 0001 1001 0ssd dddd +// Move value from data memory pointed by addressing register $S to register $D. +// Increment register $S. +// FIXME: Perform additional operation depending on destination register. +void lrri(const UDSPInstruction& opc) +{ + u8 sreg = (opc.hex >> 5) & 0x3; + u8 dreg = opc.hex & 0x1f; + + u16 val = dsp_dmem_read(g_dsp.r[sreg]); + dsp_op_write_reg(dreg, val); + g_dsp.r[sreg]++; + +} + +// LRRN $D, @$S +// 0001 1001 1ssd dddd +// Move value from data memory pointed by addressing register $S to register $D. +// Add indexing register $(0x4+S) to register $S. +// FIXME: Perform additional operation depending on destination register. +void lrrn(const UDSPInstruction& opc) +{ + u8 sreg = (opc.hex >> 5) & 0x3; + u8 dreg = opc.hex & 0x1f; + + u16 val = dsp_dmem_read(g_dsp.r[sreg]); + dsp_op_write_reg(dreg, val); + g_dsp.r[sreg] += g_dsp.r[sreg + 4]; +} + +// SRR @$D, $S +// 0001 1010 0dds ssss +// Store value from source register $S to a memory location pointed by +// addressing register $D. +// FIXME: Perform additional operation depending on source register. void srr(const UDSPInstruction& opc) { u8 dreg = (opc.hex >> 5) & 0x3; @@ -243,25 +283,51 @@ void srr(const UDSPInstruction& opc) u16 val = dsp_op_read_reg(sreg); dsp_dmem_write(g_dsp.r[dreg], val); +} +// SRRD @$D, $S +// 0001 1010 1dds ssss +// Store value from source register $S to a memory location pointed by +// addressing register $D. Decrement register $D. +// FIXME: Perform additional operation depending on source register. +void srrd(const UDSPInstruction& opc) +{ + u8 dreg = (opc.hex >> 5) & 0x3; + u8 sreg = opc.hex & 0x1f; - // post processing of dest reg - switch ((opc.hex >> 7) & 0x3) - { - case 0x0: // SRR - break; + u16 val = dsp_op_read_reg(sreg); + dsp_dmem_write(g_dsp.r[dreg], val); + g_dsp.r[dreg]--; +} - case 0x1: // SRRD - g_dsp.r[dreg]--; - break; +// SRRI @$D, $S +// 0001 1011 0dds ssss +// Store value from source register $S to a memory location pointed by +// addressing register $D. Increment register $D. +// FIXME: Perform additional operation depending on source register. +void srri(const UDSPInstruction& opc) +{ + u8 dreg = (opc.hex >> 5) & 0x3; + u8 sreg = opc.hex & 0x1f; - case 0x2: // SRRI - g_dsp.r[dreg]++; - break; + u16 val = dsp_op_read_reg(sreg); + dsp_dmem_write(g_dsp.r[dreg], val); + g_dsp.r[dreg]++; +} - case 0x3: // SRRX - g_dsp.r[dreg] += g_dsp.r[dreg + 4]; - break; - } +// SRRN @$D, $S +// 0001 1011 1dds ssss +// Store value from source register $S to a memory location pointed by +// addressing register $D. Add indexing register $(0x4+D) to register $D. + +// FIXME: Perform additional operation depending on source register. +void srrn(const UDSPInstruction& opc) +{ + u8 dreg = (opc.hex >> 5) & 0x3; + u8 sreg = opc.hex & 0x1f; + + u16 val = dsp_op_read_reg(sreg); + dsp_dmem_write(g_dsp.r[dreg], val); + g_dsp.r[dreg] += g_dsp.r[dreg + 4]; } // FIXME inside @@ -1354,13 +1420,25 @@ void msubc(const UDSPInstruction& opc) dsp_set_long_prod(prod); } +// SRS @M, $(0x18+S) +// 0010 1sss mmmm mmmm +// Store value from register $(0x18+S) to a memory pointed by address M. +// (8-bit sign extended). +// FIXME: Perform additional operation depending on destination register. +// Note: pc+=2 in doddie's doc seems wrong void srs(const UDSPInstruction& opc) { u8 reg = ((opc.hex >> 8) & 0x7) + 0x18; u16 addr = (s8)opc.hex; - dsp_dmem_write(addr, g_dsp.r[reg]); + dsp_dmem_write(addr, g_dsp.r[reg]); } - + +// LRS $(0x18+D), @M +// 0010 0ddd mmmm mmmm +// Move value from data memory pointed by address M (8-bit sign +// extended) to register $(0x18+D). +// FIXME: Perform additional operation depending on destination register. +// Note: pc+=2 in doddie's doc seems wrong void lrs(const UDSPInstruction& opc) { u8 reg = ((opc.hex >> 8) & 0x7) + 0x18; diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h index c8466b0b70..2505096091 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPInterpreter.h @@ -41,7 +41,13 @@ void bloop(const UDSPInstruction& opc); void bloopi(const UDSPInstruction& opc); void mrr(const UDSPInstruction& opc); void lrr(const UDSPInstruction& opc); +void lrrd(const UDSPInstruction& opc); +void lrri(const UDSPInstruction& opc); +void lrrn(const UDSPInstruction& opc); void srr(const UDSPInstruction& opc); +void srrd(const UDSPInstruction& opc); +void srri(const UDSPInstruction& opc); +void srrn(const UDSPInstruction& opc); void lri(const UDSPInstruction& opc); void lris(const UDSPInstruction& opc); void lr(const UDSPInstruction& opc); diff --git a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp index 38c9caf8ff..c44b31315a 100644 --- a/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp +++ b/Source/Plugins/Plugin_DSP_LLE-testing/Src/DSPTables.cpp @@ -185,21 +185,24 @@ DSPOPCTemplate opcodes[] = {"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL}, // load and store value pointed by indexing reg and increment; LRR/SRR variants - {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, - {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, - {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, {"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, - {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, - {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, - {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, - {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + {"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, + {"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, + {"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL}, + {"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + {"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + {"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + {"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + + // LOOPS + {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, + {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL}, {"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL}, {"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL}, - {"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL}, - {"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL}, - {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL}, + {"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL}, + // opcodes that can be extended // extended opcodes, note size of opcode will be set to 0