DSPLLE - 2 new opcodes (TSTPROD,MULAXH)

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@5104 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Marko Pusljar 2010-02-22 00:22:04 +00:00
parent 1824b5b25a
commit 74a6b5638f
4 changed files with 27 additions and 6 deletions

View file

@ -82,7 +82,7 @@ void mv(const UDSPInstruction& opc)
u8 sreg = opc.hex & 0x3;
u8 dreg = ((opc.hex >> 2) & 0x3);
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg + DSP_REG_ACC0]);
writeToBackLog(0, dreg + DSP_REG_AXL0, g_dsp.r[sreg + DSP_REG_ACL0]);
}
// S @$D, $acD.l
@ -92,7 +92,7 @@ void mv(const UDSPInstruction& opc)
void s(const UDSPInstruction& opc)
{
u8 dreg = opc.hex & 0x3;
u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACL0;
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
writeToBackLog(0, dreg, dsp_increment_addr_reg(dreg));
@ -105,7 +105,7 @@ void s(const UDSPInstruction& opc)
void sn(const UDSPInstruction& opc)
{
u8 dreg = opc.hex & 0x3;
u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACL0;
dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);

View file

@ -161,6 +161,8 @@ void andf(const UDSPInstruction& opc);
void xori(const UDSPInstruction& opc);
void andi(const UDSPInstruction& opc);
void ori(const UDSPInstruction& opc);
void mulaxh(const UDSPInstruction& opc);
void tstprod(const UDSPInstruction& opc);
// FIXME inside
void srbith(const UDSPInstruction& opc);

View file

@ -224,11 +224,11 @@ const DSPOPCTemplate opcodes[] =
//8
{"NX", 0x8000, 0xf700, DSPInterpreter::nx, nop, 1 | P_EXT, 0, {}, true},
{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true}, // clear acc0
{"CLR", 0x8100, 0xf700, DSPInterpreter::clr, nop, 1 | P_EXT, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true},
{"CMP", 0x8200, 0xff00, DSPInterpreter::cmp, nop, 1 | P_EXT, 0, {}, true},
//0x8300 - unknown - not used atm - could be cmp(acc1-acc0)
{"MULAXH", 0x8300, 0xff00, DSPInterpreter::mulaxh, nop, 1 | P_EXT, 0, {}, true},
{"CLRP", 0x8400, 0xff00, DSPInterpreter::clrp, nop, 1 | P_EXT, 0, {}, true},
//0x8500 - unknown mul opcode (modifies prod regs) - not used atm
{"TSTPROD", 0x8500, 0xff00, DSPInterpreter::tstprod, nop, 1 | P_EXT, 0, {}, true},
{"TSTAXH", 0x8600, 0xfe00, DSPInterpreter::tstaxh, nop, 1 | P_EXT, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true},
{"M2", 0x8a00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},
{"M0", 0x8b00, 0xff00, DSPInterpreter::srbith, nop, 1 | P_EXT, 0, {}, true},

View file

@ -158,6 +158,25 @@ void movpz(const UDSPInstruction& opc)
Update_SR_Register64(acc);
}
// MULAXH
// 1000 0011 xxxx xxxx
// Multiply $ax0.h by $ax0.h
void mulaxh(const UDSPInstruction& opc)
{
s64 prod = dsp_multiply(dsp_get_ax_h(0), dsp_get_ax_h(0));
zeroWriteBackLog();
dsp_set_long_prod(prod);
}
// TSTPROD
// 1000 0101 xxxx xxxx
// Test prod regs value.
void tstprod(const UDSPInstruction& opc)
{
s64 prod = dsp_get_long_prod();
Update_SR_Register64(prod);
zeroWriteBackLog();
}
// MULC $acS.m, $axT.h
// 110s t000 xxxx xxxx