Merge pull request #2944 from degasus/arm

JitArm64: Cleanup floating point regcache

Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp

@@ -23,9 +23,8 @@ void JitArm64::fabsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
 }
@@ -37,11 +36,10 @@ void JitArm64::faddsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 
 	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }
@@ -53,11 +51,10 @@ void JitArm64::faddx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }
@@ -69,12 +66,11 @@ void JitArm64::fmaddsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
@@ -90,12 +86,11 @@ void JitArm64::fmaddx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FMADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
 }
@@ -107,10 +102,9 @@ void JitArm64::fmrx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b);
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.INS(64, VD, 0, VB, 0);
 }
@@ -122,12 +116,11 @@ void JitArm64::fmsubsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
@@ -143,12 +136,11 @@ void JitArm64::fmsubx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FNMSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
 }
@@ -160,11 +152,10 @@ void JitArm64::fmulsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == c, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 
 	m_float_emit.FMUL(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
 }
@@ -176,11 +167,10 @@ void JitArm64::fmulx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == c);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FMUL(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
 }
@@ -192,10 +182,9 @@ void JitArm64::fnabsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b);
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FABS(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
 	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VD));
@@ -208,10 +197,9 @@ void JitArm64::fnegx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b);
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FNEG(EncodeRegToDouble(VD), EncodeRegToDouble(VB));
 }
@@ -223,12 +211,11 @@ void JitArm64::fnmaddsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
@@ -245,12 +232,11 @@ void JitArm64::fnmaddx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FNMADD(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
 }
@@ -262,12 +248,11 @@ void JitArm64::fnmsubsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(EncodeRegToDouble(V0), EncodeRegToDouble(VA), EncodeRegToDouble(VC));
@@ -284,12 +269,11 @@ void JitArm64::fnmsubx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
 	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FMSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VC), EncodeRegToDouble(VB));
 }
@@ -301,12 +285,11 @@ void JitArm64::fselx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c);
 
-	ARM64Reg VD = fpr.R(d, REG_IS_LOADED);
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VC = fpr.R(c);
+	ARM64Reg VC = fpr.R(c, REG_IS_LOADED);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FCMPE(EncodeRegToDouble(VA));
 	m_float_emit.FCSEL(EncodeRegToDouble(VD), EncodeRegToDouble(VC), EncodeRegToDouble(VB), CC_GE);
@@ -319,11 +302,10 @@ void JitArm64::fsubsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 
 	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }
@@ -335,11 +317,10 @@ void JitArm64::fsubx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FSUB(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }
@@ -350,10 +331,9 @@ void JitArm64::frspx(UGeckoInstruction inst)
 	JITDISABLE(bJITFloatingPointOff);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b, REG_DUP);
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 
 	m_float_emit.FCVTN(32, EncodeRegToDouble(VD), EncodeRegToDouble(VB));
 	m_float_emit.FCVTL(64, EncodeRegToDouble(VD), EncodeRegToDouble(VD));
@@ -451,10 +431,9 @@ void JitArm64::fctiwzx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b);
 
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	ARM64Reg V0 = fpr.GetReg();
 
@@ -475,11 +454,10 @@ void JitArm64::fdivx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d);
+	ARM64Reg VD = fpr.RW(d);
 
 	m_float_emit.FDIV(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }
@@ -491,11 +469,10 @@ void JitArm64::fdivsx(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_DUP);
 
 	ARM64Reg VA = fpr.R(a, REG_IS_LOADED);
 	ARM64Reg VB = fpr.R(b, REG_IS_LOADED);
-	ARM64Reg VD = fpr.R(d, REG_DUP);
+	ARM64Reg VD = fpr.RW(d, REG_DUP);
 
 	m_float_emit.FDIV(EncodeRegToDouble(VD), EncodeRegToDouble(VA), EncodeRegToDouble(VB));
 }

Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp

@@ -73,9 +73,7 @@ void JitArm64::lfXX(UGeckoInstruction inst)
 
 	RegType type = !!(flags & BackPatchInfo::FLAG_SIZE_F64) ? REG_LOWER_PAIR : REG_DUP;
 
-	fpr.BindToRegister(inst.FD, false, type);
+	ARM64Reg VD = fpr.RW(inst.FD, type);
-
-	ARM64Reg VD = fpr.R(inst.FD, type);
 	ARM64Reg addr_reg = W0;
 
 	gpr.Lock(W0, W30);

Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp

@@ -66,8 +66,7 @@ void JitArm64::psq_l(UGeckoInstruction inst)
 	LDR(X30, X30, ArithOption(EncodeRegTo64(type_reg), true));
 	BLR(X30);
 
-	fpr.BindToRegister(inst.RS, false, REG_REG);
+	ARM64Reg VS = fpr.RW(inst.RS, REG_REG);
-	ARM64Reg VS = fpr.R(inst.RS, REG_REG);
 	m_float_emit.FCVTL(64, VS, D0);
 	if (inst.W)
 	{

Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp

@@ -23,10 +23,9 @@ void JitArm64::ps_abs(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b, REG_REG);
 
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FABS(64, VD, VB);
 }
@@ -38,11 +37,10 @@ void JitArm64::ps_add(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FADD(64, VD, VA, VB);
 }
@@ -54,11 +52,10 @@ void JitArm64::ps_div(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FDIV(64, VD, VA, VB);
 }
@@ -70,12 +67,11 @@ void JitArm64::ps_madd(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(64, V0, VA, VC);
@@ -91,12 +87,11 @@ void JitArm64::ps_madds0(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VC, 0);
@@ -113,12 +108,11 @@ void JitArm64::ps_madds1(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VC, 1);
@@ -135,11 +129,10 @@ void JitArm64::ps_merge00(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.TRN1(64, VD, VA, VB);
 }
@@ -151,11 +144,10 @@ void JitArm64::ps_merge01(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.INS(64, VD, 0, VA, 0);
 	m_float_emit.INS(64, VD, 1, VB, 1);
@@ -168,11 +160,10 @@ void JitArm64::ps_merge10(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	if (d != a && d != b)
 	{
@@ -196,11 +187,10 @@ void JitArm64::ps_merge11(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.TRN2(64, VD, VA, VB);
 }
@@ -216,10 +206,8 @@ void JitArm64::ps_mr(UGeckoInstruction inst)
 	if (d == b)
 		return;
 
-	fpr.BindToRegister(d, REG_REG, REG_REG);
-
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.ORR(VD, VB, VB);
 }
@@ -231,11 +219,10 @@ void JitArm64::ps_mul(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FMUL(64, VD, VA, VC);
 }
@@ -247,11 +234,10 @@ void JitArm64::ps_muls0(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VC, 0);
@@ -266,11 +252,10 @@ void JitArm64::ps_muls1(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VC, 1);
@@ -285,12 +270,11 @@ void JitArm64::ps_msub(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(64, V0, VA, VC);
@@ -306,10 +290,9 @@ void JitArm64::ps_nabs(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b, REG_REG);
 
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FABS(64, VD, VB);
 	m_float_emit.FNEG(64, VD, VD);
@@ -322,10 +305,9 @@ void JitArm64::ps_neg(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b, REG_REG);
 
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FNEG(64, VD, VB);
 }
@@ -337,12 +319,11 @@ void JitArm64::ps_nmadd(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(64, V0, VA, VC);
@@ -359,12 +340,11 @@ void JitArm64::ps_nmsub(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.FMUL(64, V0, VA, VC);
@@ -381,10 +361,9 @@ void JitArm64::ps_res(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == b, REG_REG);
 
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FRSQRTE(64, VD, VB);
 }
@@ -396,12 +375,11 @@ void JitArm64::ps_sel(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	if (d != a && d != b && d != c)
 	{
@@ -425,11 +403,10 @@ void JitArm64::ps_sub(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 
 	m_float_emit.FSUB(64, VD, VA, VB);
 }
@@ -441,12 +418,11 @@ void JitArm64::ps_sum0(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VB, 1);
@@ -471,12 +447,11 @@ void JitArm64::ps_sum1(UGeckoInstruction inst)
 	FALLBACK_IF(inst.Rc);
 
 	u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
-	fpr.BindToRegister(d, d == a || d == b || d == c, REG_REG);
 
 	ARM64Reg VA = fpr.R(a, REG_REG);
 	ARM64Reg VB = fpr.R(b, REG_REG);
 	ARM64Reg VC = fpr.R(c, REG_REG);
-	ARM64Reg VD = fpr.R(d, REG_REG);
+	ARM64Reg VD = fpr.RW(d, REG_REG);
 	ARM64Reg V0 = fpr.GetReg();
 
 	m_float_emit.DUP(64, V0, VA, 0);

Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp

@@ -331,11 +331,6 @@ ARM64Reg Arm64FPRCache::R(u32 preg, RegType type)
 			// Change it over to a full 128bit register
 			reg.LoadToReg(reg.GetReg());
 		}
-		else if (type == REG_DUP)
-		{
-			// We already only have the lower 64bits
-			// Don't do anything
-		}
 		return reg.GetReg();
 	}
 	break;
@@ -350,16 +345,6 @@ ARM64Reg Arm64FPRCache::R(u32 preg, RegType type)
 			m_float_emit->INS(64, host_reg, 1, host_reg, 0);
 			reg.LoadToReg(host_reg);
 		}
-		else if (type == REG_LOWER_PAIR)
-		{
-			// We are only requesting the lower 64bits of a pair
-			// We've got to be careful in this instance
-			// Store our current duplicated high bits to the file
-			// then convert over to a lower reg
-			if (reg.IsDirty())
-				m_float_emit->STR(64, INDEX_UNSIGNED, host_reg, X29, PPCSTATE_OFF(ps[preg][1]));
-			reg.LoadLowerReg(host_reg);
-		}
 		return host_reg;
 	}
 	break;
@@ -367,21 +352,16 @@ ARM64Reg Arm64FPRCache::R(u32 preg, RegType type)
 	{
 		ARM64Reg host_reg = GetReg();
 		u32 load_size;
-		if (type == REG_LOWER_PAIR)
+		if (type == REG_REG)
-		{
-			load_size = 64;
-			reg.LoadLowerReg(host_reg);
-		}
-		else if (type == REG_DUP)
-		{
-			load_size = 64;
-			reg.LoadDup(host_reg);
-		}
-		else
 		{
 			load_size = 128;
 			reg.LoadToReg(host_reg);
 		}
+		else
+		{
+			load_size = 64;
+			reg.LoadLowerReg(host_reg);
+		}
 		reg.SetDirty(false);
 		m_float_emit->LDR(load_size, INDEX_UNSIGNED, host_reg, X29, PPCSTATE_OFF(ps[preg][0]));
 		return host_reg;
@@ -395,12 +375,13 @@ ARM64Reg Arm64FPRCache::R(u32 preg, RegType type)
 	return INVALID_REG;
 }
 
-void Arm64FPRCache::BindToRegister(u32 preg, bool do_load, RegType type)
+ARM64Reg Arm64FPRCache::RW(u32 preg, RegType type)
 {
 	OpArg& reg = m_guest_registers[preg];
 
 	bool was_dirty = reg.IsDirty();
 
+	IncrementAllUsed();
 	reg.ResetLastUsed();
 
 	reg.SetDirty(true);
@@ -409,26 +390,18 @@ void Arm64FPRCache::BindToRegister(u32 preg, bool do_load, RegType type)
 	case REG_NOTLOADED:
 	{
 		ARM64Reg host_reg = GetReg();
-		u32 load_size;
 		if (type == REG_LOWER_PAIR)
 		{
-			// We only want the lower 64bits
-			load_size = 64;
 			reg.LoadLowerReg(host_reg);
 		}
 		else if (type == REG_DUP)
 		{
-			load_size = 64;
 			reg.LoadDup(host_reg);
 		}
 		else
 		{
-			// We want the full 128bit register
-			load_size = 128;
 			reg.LoadToReg(host_reg);
 		}
-		if (do_load)
-			m_float_emit->LDR(load_size, INDEX_UNSIGNED, host_reg, X29, PPCSTATE_OFF(ps[preg][0]));
 	}
 	break;
 	case REG_LOWER_PAIR:
@@ -436,16 +409,6 @@ void Arm64FPRCache::BindToRegister(u32 preg, bool do_load, RegType type)
 		ARM64Reg host_reg = reg.GetReg();
 		if (type == REG_REG)
 		{
-			// Okay, we've got the lower reg loaded and we really wanted the full register
-			if (do_load)
-			{
-				// Load the high 64bits from the file and insert them in to the high 64bits of the host register
-				ARM64Reg tmp_reg = GetReg();
-				m_float_emit->LDR(64, INDEX_UNSIGNED, tmp_reg, X29, PPCSTATE_OFF(ps[preg][1]));
-				m_float_emit->INS(64, host_reg, 1, tmp_reg, 0);
-				UnlockRegister(tmp_reg);
-			}
-
 			// Change it over to a full 128bit register
 			reg.LoadToReg(host_reg);
 		}
@@ -505,6 +468,8 @@ void Arm64FPRCache::BindToRegister(u32 preg, bool do_load, RegType type)
 		// Do nothing
 	break;
 	}
+
+	return reg.GetReg();
 }
 
 void Arm64FPRCache::GetAllocationOrder()

Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.h

@@ -275,7 +275,7 @@ public:
 	// Will dump an immediate to the host register as well
 	ARM64Reg R(u32 preg, RegType type = REG_LOWER_PAIR);
 
-	void BindToRegister(u32 preg, bool do_load, RegType type = REG_LOWER_PAIR);
+	ARM64Reg RW(u32 preg, RegType type = REG_LOWER_PAIR);
 
 	BitSet32 GetCallerSavedUsed() override;