From 86de3df07212fde67eb96a86bd83d3707b984619 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sat, 5 Jun 2021 23:15:08 +0200 Subject: [PATCH] JitArm64: Discard top 32 bits in slwx result srwx would like to be able to assume that the top 32 bits are zero, and cmpl is already doing so. --- .../Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 4e45b3d5c9..568a3e0eeb 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -1451,15 +1451,12 @@ void JitArm64::slwx(UGeckoInstruction inst) { gpr.BindToRegister(a, a == b || a == s); - // PowerPC any shift in the 32-63 register range results in zero - // Since it has 32bit registers - // AArch64 it will use a mask of the register size for determining what shift amount - // So if we use a 64bit so the bits will end up in the high 32bits, and - // Later instructions will just eat high 32bits since it'll run 32bit operations for everything. + // On PowerPC, shifting a 32-bit register by an amount from 32 to 63 results in 0. + // We emulate this by using a 64-bit operation and then discarding the top 32 bits. LSLV(EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(s)), EncodeRegTo64(gpr.R(b))); - if (inst.Rc) ComputeRC0(gpr.R(a)); + MOV(gpr.R(a), gpr.R(a)); } } @@ -1499,10 +1496,6 @@ void JitArm64::srwx(UGeckoInstruction inst) { gpr.BindToRegister(a, a == b || a == s); - // wipe upper bits. TODO: get rid of it, but then no instruction is allowed to emit some higher - // bits. - MOV(gpr.R(s), gpr.R(s)); - LSRV(EncodeRegTo64(gpr.R(a)), EncodeRegTo64(gpr.R(s)), EncodeRegTo64(gpr.R(b))); if (inst.Rc)