mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-09-20 11:21:43 +02:00
DSPLLE: Improve various instruction comments
* DSP*Arithmetic: Fix grammar for ANDCF and ANDF
* DSP*Arithmetic: Fix registers used by MOVAX and MOV
* DSP*Branch: Fix documentation for JMPR
* DSP*Branch: Fix HALT encoding ("I think I saw a two")
* DSP*ExtOps: Fix 'LN encoding (The listed encoding was for 'L)
* DSP*ExtOps: Improve documentation for 'LD and 'LDAX
* DSPJitExtOps: Correct typo
* DSP*LoadStore: Remove obsolete comment about pc in SRS (This was fixed in 1419e7e5b2)
* DSP*LoadStore: Fix comments for LRR/SRR
* DSP*Misc: Improve documentation for SBCLR and SBSET
* DSP*Multiplier: Fix MULXAC encoding (The previous encoding was for MULXMVZ)
* DSP*Multiplier: Fix tabs in MULCAC and MULCMVZ (There are some other tabs in comments in the JIT, but these are the only ones that are in instruction comments instead of indicating the corresponding interpreter code. Those other comments can be corrected in a different PR, as they're not documentation related.)
* DSPJitMultiplier: Fix MULXMVZ typo
This commit is contained in:
Pokechu22
parent
ddc2dd91d2
commit
88d2a7260d
12 changed files with 104 additions and 96 deletions
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@ -47,7 +47,7 @@ void Interpreter::clrl(const UDSPInstruction opc)
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// 0000 001r 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal I.
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// accumulator mid part $acD.m with immediate value I is equal to I.
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//
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// flags out: -x-- ----
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void Interpreter::andcf(const UDSPInstruction opc)
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@ -64,7 +64,7 @@ void Interpreter::andcf(const UDSPInstruction opc)
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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// immediate value 0.
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// to immediate value 0.
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//
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// flags out: -x-- ----
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void Interpreter::andf(const UDSPInstruction opc)
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@ -793,7 +793,7 @@ void Interpreter::movr(const UDSPInstruction opc)
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// MOVAX $acD, $axS
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// 0110 10sd xxxx xxxx
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// Moves secondary accumulator $axS to accumulator $axD.
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// Moves secondary accumulator $axS to accumulator $acD.
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//
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// flags out: --xx xx00
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void Interpreter::movax(const UDSPInstruction opc)
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@ -811,7 +811,7 @@ void Interpreter::movax(const UDSPInstruction opc)
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// MOV $acD, $ac(1-D)
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// 0110 110d xxxx xxxx
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// Moves accumulator $ax(1-D) to accumulator $axD.
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// Moves accumulator $ac(1-D) to accumulator $acD.
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//
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// flags out: --x0 xx00
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void Interpreter::mov(const UDSPInstruction opc)
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@ -76,9 +76,10 @@ void Interpreter::jcc(const UDSPInstruction opc)
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}
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// Generic jmpr implementation
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// JMPcc $R
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// JRcc $R
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// 0001 0111 rrr0 cccc
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// Jump to address; set program counter to a value from register $R.
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// Jump to address if condition cc has been met. Set program counter to
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// a value from register $R.
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void Interpreter::jmprcc(const UDSPInstruction opc)
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{
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if (!CheckCondition(opc & 0xf))
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@ -116,7 +117,7 @@ void Interpreter::rti(const UDSPInstruction)
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}
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// HALT
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// 0000 0000 0020 0001
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// 0000 0000 0010 0001
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// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
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void Interpreter::halt(const UDSPInstruction)
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{
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@ -144,7 +144,7 @@ void Interpreter::l(const UDSPInstruction opc)
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}
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// LN $axD.D, @$arS
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// xxxx xxxx 01dd d0ss
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// xxxx xxxx 01dd d1ss
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// Load $axD.D/$acD.D with value from memory pointed by register $arS.
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// Add indexing register $ixS to register $arS.
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void Interpreter::ln(const UDSPInstruction opc)
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@ -327,17 +327,17 @@ void Interpreter::slnm(const UDSPInstruction opc)
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IncreaseAddressRegister(DSP_REG_AR0, static_cast<s16>(state.r.ix[0])));
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}
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// LD $ax0.d, $ax1.r, @$arS
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// LD $ax0.D, $ax1.R, @$arS
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// xxxx xxxx 11dr 00ss
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// example for "nx'ld $AX0.L, $AX1.L, @$AR3"
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// Loads the word pointed by AR0 to AX0.H, then loads the word pointed by AR3 to AX0.L.
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// Increments AR0 and AR3.
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// If AR0 and AR3 point into the same memory page (upper 6 bits of addr are the same -> games are
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// not doing that!)
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// then the value pointed by AR0 is loaded to BOTH AX0.H and AX0.L.
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// If AR0 points into an invalid memory page (ie 0x2000), then AX0.H keeps its old value. (not
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// Load register $ax0.D (either $ax0.l or $ax0.h) with value from memory pointed by register $arS.
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// Load register $ax1.R (either $ax1.l or $ax1.h) with value from memory pointed by register $ar3.
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// Increment both $arS and $ar3.
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// S cannot be 3, as that encodes LDAX. Thus $arS and $ar3 are known to be distinct.
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// If $ar0 and $ar3 point into the same memory page (upper 6 bits of addr are the same -> games are
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// not doing that!) then the value pointed by $ar0 is loaded to BOTH $ax0.D and $ax1.R.
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// If $ar0 points into an invalid memory page (ie 0x2000), then $ax0.D keeps its old value. (not
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// implemented yet)
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// If AR3 points into an invalid memory page, then AX0.L gets the same value as AX0.H. (not
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// If $ar3 points into an invalid memory page, then $ax1.R gets the same value as $ax0.D. (not
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// implemented yet)
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void Interpreter::ld(const UDSPInstruction opc)
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{
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@ -360,6 +360,9 @@ void Interpreter::ld(const UDSPInstruction opc)
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// LDAX $axR, @$arS
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// xxxx xxxx 11sr 0011
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// Load register $axR.h with value from memory pointed by register $arS.
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// Load register $axR.l with value from memory pointed by register $ar3.
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// Increment both $arS and $ar3.
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void Interpreter::ldax(const UDSPInstruction opc)
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{
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const u8 sreg = (opc >> 5) & 0x1;
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@ -378,7 +381,7 @@ void Interpreter::ldax(const UDSPInstruction opc)
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WriteToBackLog(3, DSP_REG_AR3, IncrementAddressRegister(DSP_REG_AR3));
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}
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// LDN $ax0.d, $ax1.r, @$arS
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// LDN $ax0.D, $ax1.R, @$arS
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// xxxx xxxx 11dr 01ss
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void Interpreter::ldn(const UDSPInstruction opc)
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{
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@ -419,7 +422,7 @@ void Interpreter::ldaxn(const UDSPInstruction opc)
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WriteToBackLog(3, DSP_REG_AR3, IncrementAddressRegister(DSP_REG_AR3));
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}
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// LDM $ax0.d, $ax1.r, @$arS
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// LDM $ax0.D, $ax1.R, @$arS
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// xxxx xxxx 11dr 10ss
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void Interpreter::ldm(const UDSPInstruction opc)
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{
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@ -462,7 +465,7 @@ void Interpreter::ldaxm(const UDSPInstruction opc)
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IncreaseAddressRegister(DSP_REG_AR3, static_cast<s16>(state.r.ix[3])));
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}
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// LDNM $ax0.d, $ax1.r, @$arS
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// LDNM $ax0.D, $ax1.R, @$arS
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// xxxx xxxx 11dr 11ss
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void Interpreter::ldnm(const UDSPInstruction opc)
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{
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@ -13,7 +13,6 @@ namespace DSP::Interpreter
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// Move value from register $(0x18+S) to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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// Note: pc+=2 in duddie's doc seems wrong
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void Interpreter::srs(const UDSPInstruction opc)
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{
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auto& state = m_dsp_core.DSPState();
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@ -86,9 +85,9 @@ void Interpreter::si(const UDSPInstruction opc)
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state.WriteDMEM(addr, imm);
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}
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// LRR $D, @$S
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// LRR $D, @$arS
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// 0001 1000 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Move value from data memory pointed by addressing register $arS to register $D.
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void Interpreter::lrr(const UDSPInstruction opc)
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{
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const u8 sreg = (opc >> 5) & 0x3;
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@ -100,10 +99,10 @@ void Interpreter::lrr(const UDSPInstruction opc)
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ConditionalExtendAccum(dreg);
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}
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// LRRD $D, @$S
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// LRRD $D, @$arS
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// 0001 1000 1ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Decrement register $S.
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// Move value from data memory pointed by addressing register $arS to register $D.
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// Decrement register $arS.
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void Interpreter::lrrd(const UDSPInstruction opc)
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{
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const u8 sreg = (opc >> 5) & 0x3;
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@ -116,10 +115,10 @@ void Interpreter::lrrd(const UDSPInstruction opc)
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state.r.ar[sreg] = DecrementAddressRegister(sreg);
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}
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// LRRI $D, @$S
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// LRRI $D, @$arS
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// 0001 1001 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Increment register $S.
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// Move value from data memory pointed by addressing register $arS to register $D.
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// Increment register $arS.
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void Interpreter::lrri(const UDSPInstruction opc)
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{
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const u8 sreg = (opc >> 5) & 0x3;
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@ -132,10 +131,10 @@ void Interpreter::lrri(const UDSPInstruction opc)
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state.r.ar[sreg] = IncrementAddressRegister(sreg);
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}
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// LRRN $D, @$S
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// LRRN $D, @$arS
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// 0001 1001 1ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Add indexing register $(0x4+S) to register $S.
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// Move value from data memory pointed by addressing register $arS to register $D.
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// Add corresponding indexing register $ixS to register $arS.
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void Interpreter::lrrn(const UDSPInstruction opc)
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{
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const u8 sreg = (opc >> 5) & 0x3;
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@ -148,10 +147,10 @@ void Interpreter::lrrn(const UDSPInstruction opc)
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state.r.ar[sreg] = IncreaseAddressRegister(sreg, static_cast<s16>(state.r.ix[sreg]));
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}
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// SRR @$D, $S
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// SRR @$arD, $S
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// 0001 1010 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D.
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// addressing register $arD.
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void Interpreter::srr(const UDSPInstruction opc)
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{
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const u8 dreg = (opc >> 5) & 0x3;
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@ -164,10 +163,10 @@ void Interpreter::srr(const UDSPInstruction opc)
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state.WriteDMEM(state.r.ar[dreg], OpReadRegister(sreg));
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}
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// SRRD @$D, $S
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// SRRD @$arD, $S
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// 0001 1010 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Decrement register $D.
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// addressing register $arD. Decrement register $arD.
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void Interpreter::srrd(const UDSPInstruction opc)
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{
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const u8 dreg = (opc >> 5) & 0x3;
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@ -182,10 +181,10 @@ void Interpreter::srrd(const UDSPInstruction opc)
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state.r.ar[dreg] = DecrementAddressRegister(dreg);
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}
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// SRRI @$D, $S
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// SRRI @$arD, $S
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// 0001 1011 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Increment register $D.
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// addressing register $arD. Increment register $arD.
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void Interpreter::srri(const UDSPInstruction opc)
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{
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const u8 dreg = (opc >> 5) & 0x3;
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@ -200,10 +199,10 @@ void Interpreter::srri(const UDSPInstruction opc)
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state.r.ar[dreg] = IncrementAddressRegister(dreg);
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}
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// SRRN @$D, $S
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// SRRN @$arD, $S
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// 0001 1011 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Add DSP_REG_IX0 register to register $D.
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// addressing register $arD. Add corresponding indexing register $ixD to register $arD.
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void Interpreter::srrn(const UDSPInstruction opc)
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{
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const u8 dreg = (opc >> 5) & 0x3;
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@ -122,8 +122,8 @@ void Interpreter::addarn(const UDSPInstruction opc)
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// SBCLR #I
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// 0001 0010 aaaa aiii
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// bit of status register $sr. Bit number is calculated by adding 6 to
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// immediate value I.
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// Clear bit of status register $sr. Bit number is calculated by adding 6 to immediate value I;
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// thus, bits 6 through 13 (LZ through AM) can be cleared with this instruction.
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void Interpreter::sbclr(const UDSPInstruction opc)
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{
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auto& state = m_dsp_core.DSPState();
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@ -134,8 +134,8 @@ void Interpreter::sbclr(const UDSPInstruction opc)
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// SBSET #I
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// 0001 0011 aaaa aiii
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// Set bit of status register $sr. Bit number is calculated by adding 6 to
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// immediate value I.
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// Set bit of status register $sr. Bit number is calculated by adding 6 to immediate value I;
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// thus, bits 6 through 13 (LZ through AM) can be set with this instruction.
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void Interpreter::sbset(const UDSPInstruction opc)
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{
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auto& state = m_dsp_core.DSPState();
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@ -247,7 +247,7 @@ void Interpreter::mulx(const UDSPInstruction opc)
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}
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// MULXAC $ax0.S, $ax1.T, $acR
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// 101s t01r xxxx xxxx
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// 101s t10r xxxx xxxx
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// Add product register to accumulator register $acR. Multiply one part
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// $ax0 by one part $ax1. Part is selected by S and
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// T bits. Zero selects low part, one selects high part.
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@ -343,7 +343,7 @@ void Interpreter::mulc(const UDSPInstruction opc)
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}
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// MULCAC $acS.m, $axT.h, $acR
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// 110s t10r xxxx xxxx
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// 110s t10r xxxx xxxx
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// Multiply mid part of accumulator register $acS.m by high part $axS.h of
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// secondary accumulator $axS (treat them both as signed). Add product
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// register before multiplication to accumulator $acR.
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@ -393,7 +393,7 @@ void Interpreter::mulcmv(const UDSPInstruction opc)
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}
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// MULCMVZ $acS.m, $axT.h, $acR
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// 110s t01r xxxx xxxx
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// 110s t01r xxxx xxxx
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// Multiply mid part of accumulator register $acS.m by high part $axT.h of
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// secondary accumulator $axT (treat them both as signed). Move product
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// register before multiplication to accumulator $acR, set (round) low part of
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@ -56,7 +56,7 @@ void DSPEmitter::clrl(const UDSPInstruction opc)
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// 0000 001r 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal I.
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// accumulator mid part $acD.m with immediate value I is equal to I.
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//
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// flags out: -x-- ----
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void DSPEmitter::andcf(const UDSPInstruction opc)
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@ -91,7 +91,7 @@ void DSPEmitter::andcf(const UDSPInstruction opc)
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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// immediate value 0.
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// to immediate value 0.
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//
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// flags out: -x-- ----
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void DSPEmitter::andf(const UDSPInstruction opc)
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@ -1089,7 +1089,7 @@ void DSPEmitter::movr(const UDSPInstruction opc)
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// MOVAX $acD, $axS
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// 0110 10sd xxxx xxxx
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// Moves secondary accumulator $axS to accumulator $axD.
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// Moves secondary accumulator $axS to accumulator $acD.
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//
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// flags out: --xx xx00
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void DSPEmitter::movax(const UDSPInstruction opc)
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@ -1110,7 +1110,7 @@ void DSPEmitter::movax(const UDSPInstruction opc)
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// MOV $acD, $ac(1-D)
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// 0110 110d xxxx xxxx
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// Moves accumulator $ax(1-D) to accumulator $axD.
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// Moves accumulator $ac(1-D) to accumulator $acD.
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//
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// flags out: --x0 xx00
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void DSPEmitter::mov(const UDSPInstruction opc)
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@ -156,9 +156,10 @@ void DSPEmitter::r_jmprcc(const UDSPInstruction opc)
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WriteBranchExit();
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}
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// Generic jmpr implementation
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// JMPcc $R
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// JRcc $R
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// 0001 0111 rrr0 cccc
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// Jump to address; set program counter to a value from register $R.
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// Jump to address if condition cc has been met. Set program counter to
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// a value from register $R.
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// NOTE: Cannot use FallBackToInterpreter(opc) here because of the need to write branch exit
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void DSPEmitter::jmprcc(const UDSPInstruction opc)
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{
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@ -270,7 +271,7 @@ void DSPEmitter::rti(const UDSPInstruction opc)
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}
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||||
|
||||
// HALT
|
||||
// 0000 0000 0020 0001
|
||||
// 0000 0000 0010 0001
|
||||
// Stops execution of DSP code. Sets bit DSP_CR_HALT in register DREG_CR.
|
||||
void DSPEmitter::halt(const UDSPInstruction)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
using namespace Gen;
|
||||
|
||||
/* It is safe to directly write to the address registers as they are
|
||||
neither read not written by any extendable opcode. The same is true
|
||||
neither read nor written by any extendable opcode. The same is true
|
||||
for memory accesses.
|
||||
It probably even is safe to write to all registers except for
|
||||
SR, ACx.x, AXx.x and PROD, which may be modified by the main op.
|
||||
|
|
@ -131,7 +131,7 @@ void DSPEmitter::l(const UDSPInstruction opc)
|
|||
}
|
||||
|
||||
// LN $axD.D, @$arS
|
||||
// xxxx xxxx 01dd d0ss
|
||||
// xxxx xxxx 01dd d1ss
|
||||
// Load $axD.D/$acD.D with value from memory pointed by register $arS.
|
||||
// Add indexing register $ixS to register $arS.
|
||||
void DSPEmitter::ln(const UDSPInstruction opc)
|
||||
|
|
@ -354,16 +354,18 @@ void DSPEmitter::slnm(const UDSPInstruction opc)
|
|||
increase_addr_reg(DSP_REG_AR0, DSP_REG_AR0);
|
||||
}
|
||||
|
||||
// LD $ax0.d, $ax1.r, @$arS
|
||||
// LD $ax0.D, $ax1.R, @$arS
|
||||
// xxxx xxxx 11dr 00ss
|
||||
// example for "nx'ld $AX0.L, $AX1.L, @$AR3"
|
||||
// Loads the word pointed by AR0 to AX0.H, then loads the word pointed by AR3
|
||||
// to AX0.L. Increments AR0 and AR3. If AR0 and AR3 point into the same
|
||||
// memory page (upper 6 bits of addr are the same -> games are not doing that!)
|
||||
// then the value pointed by AR0 is loaded to BOTH AX0.H and AX0.L. If AR0
|
||||
// points into an invalid memory page (ie 0x2000), then AX0.H keeps its old
|
||||
// value. (not implemented yet) If AR3 points into an invalid memory page, then
|
||||
// AX0.L gets the same value as AX0.H. (not implemented yet)
|
||||
// Load register $ax0.D (either $ax0.l or $ax0.h) with value from memory pointed by register $arS.
|
||||
// Load register $ax1.R (either $ax1.l or $ax1.h) with value from memory pointed by register $ar3.
|
||||
// Increment both $arS and $ar3.
|
||||
// S cannot be 3, as that encodes LDAX. Thus $arS and $ar3 are known to be distinct.
|
||||
// If $ar0 and $ar3 point into the same memory page (upper 6 bits of addr are the same -> games are
|
||||
// not doing that!) then the value pointed by $ar0 is loaded to BOTH $ax0.D and $ax1.R.
|
||||
// If $ar0 points into an invalid memory page (ie 0x2000), then $ax0.D keeps its old value. (not
|
||||
// implemented yet)
|
||||
// If $ar3 points into an invalid memory page, then $ax1.R gets the same value as $ax0.D. (not
|
||||
// implemented yet)
|
||||
void DSPEmitter::ld(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x1;
|
||||
|
|
@ -396,6 +398,9 @@ void DSPEmitter::ld(const UDSPInstruction opc)
|
|||
|
||||
// LDAX $axR, @$arS
|
||||
// xxxx xxxx 11sr 0011
|
||||
// Load register $axR.h with value from memory pointed by register $arS.
|
||||
// Load register $axR.l with value from memory pointed by register $ar3.
|
||||
// Increment both $arS and $ar3.
|
||||
void DSPEmitter::ldax(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc >> 5) & 0x1;
|
||||
|
|
@ -425,7 +430,7 @@ void DSPEmitter::ldax(const UDSPInstruction opc)
|
|||
increment_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDN $ax0.d, $ax1.r, @$arS
|
||||
// LDN $ax0.D, $ax1.R, @$arS
|
||||
// xxxx xxxx 11dr 01ss
|
||||
void DSPEmitter::ldn(const UDSPInstruction opc)
|
||||
{
|
||||
|
|
@ -488,7 +493,7 @@ void DSPEmitter::ldaxn(const UDSPInstruction opc)
|
|||
increment_addr_reg(DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDM $ax0.d, $ax1.r, @$arS
|
||||
// LDM $ax0.D, $ax1.R, @$arS
|
||||
// xxxx xxxx 11dr 10ss
|
||||
void DSPEmitter::ldm(const UDSPInstruction opc)
|
||||
{
|
||||
|
|
@ -551,7 +556,7 @@ void DSPEmitter::ldaxm(const UDSPInstruction opc)
|
|||
increase_addr_reg(DSP_REG_AR3, DSP_REG_AR3);
|
||||
}
|
||||
|
||||
// LDNM $ax0.d, $ax1.r, @$arS
|
||||
// LDNM $ax0.D, $ax1.R, @$arS
|
||||
// xxxx xxxx 11dr 11ss
|
||||
void DSPEmitter::ldnm(const UDSPInstruction opc)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@ namespace DSP::JIT::x64
|
|||
// Move value from register $(0x18+S) to data memory pointed by address
|
||||
// CR[0-7] | M. That is, the upper 8 bits of the address are the
|
||||
// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
|
||||
// Note: pc+=2 in duddie's doc seems wrong
|
||||
void DSPEmitter::srs(const UDSPInstruction opc)
|
||||
{
|
||||
u8 reg = ((opc >> 8) & 0x7) + 0x18;
|
||||
|
|
@ -105,9 +104,9 @@ void DSPEmitter::si(const UDSPInstruction opc)
|
|||
m_gpr.PutXReg(tmp1);
|
||||
}
|
||||
|
||||
// LRR $D, @$S
|
||||
// LRR $D, @$arS
|
||||
// 0001 1000 0ssd dddd
|
||||
// Move value from data memory pointed by addressing register $S to register $D.
|
||||
// Move value from data memory pointed by addressing register $arS to register $D.
|
||||
void DSPEmitter::lrr(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -124,10 +123,10 @@ void DSPEmitter::lrr(const UDSPInstruction opc)
|
|||
dsp_conditional_extend_accum(dreg);
|
||||
}
|
||||
|
||||
// LRRD $D, @$S
|
||||
// LRRD $D, @$arS
|
||||
// 0001 1000 1ssd dddd
|
||||
// Move value from data memory pointed by addressing register $S to register $D.
|
||||
// Decrement register $S.
|
||||
// Move value from data memory pointed by addressing register $arS to register $D.
|
||||
// Decrement register $arS.
|
||||
void DSPEmitter::lrrd(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -145,10 +144,10 @@ void DSPEmitter::lrrd(const UDSPInstruction opc)
|
|||
decrement_addr_reg(sreg);
|
||||
}
|
||||
|
||||
// LRRI $D, @$S
|
||||
// LRRI $D, @$arS
|
||||
// 0001 1001 0ssd dddd
|
||||
// Move value from data memory pointed by addressing register $S to register $D.
|
||||
// Increment register $S.
|
||||
// Move value from data memory pointed by addressing register $arS to register $D.
|
||||
// Increment register $arS.
|
||||
void DSPEmitter::lrri(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -166,10 +165,10 @@ void DSPEmitter::lrri(const UDSPInstruction opc)
|
|||
increment_addr_reg(sreg);
|
||||
}
|
||||
|
||||
// LRRN $D, @$S
|
||||
// LRRN $D, @$arS
|
||||
// 0001 1001 1ssd dddd
|
||||
// Move value from data memory pointed by addressing register $S to register $D.
|
||||
// Add indexing register $(0x4+S) to register $S.
|
||||
// Move value from data memory pointed by addressing register $arS to register $D.
|
||||
// Add indexing register $ixS to register $arS.
|
||||
void DSPEmitter::lrrn(const UDSPInstruction opc)
|
||||
{
|
||||
u8 sreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -187,10 +186,10 @@ void DSPEmitter::lrrn(const UDSPInstruction opc)
|
|||
increase_addr_reg(sreg, sreg);
|
||||
}
|
||||
|
||||
// SRR @$D, $S
|
||||
// SRR @$arD, $S
|
||||
// 0001 1010 0dds ssss
|
||||
// Store value from source register $S to a memory location pointed by
|
||||
// addressing register $D.
|
||||
// addressing register $arD.
|
||||
void DSPEmitter::srr(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -205,10 +204,10 @@ void DSPEmitter::srr(const UDSPInstruction opc)
|
|||
m_gpr.PutXReg(tmp1);
|
||||
}
|
||||
|
||||
// SRRD @$D, $S
|
||||
// SRRD @$arD, $S
|
||||
// 0001 1010 1dds ssss
|
||||
// Store value from source register $S to a memory location pointed by
|
||||
// addressing register $D. Decrement register $D.
|
||||
// addressing register $arD. Decrement register $arD.
|
||||
void DSPEmitter::srrd(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -225,10 +224,10 @@ void DSPEmitter::srrd(const UDSPInstruction opc)
|
|||
decrement_addr_reg(dreg);
|
||||
}
|
||||
|
||||
// SRRI @$D, $S
|
||||
// SRRI @$arD, $S
|
||||
// 0001 1011 0dds ssss
|
||||
// Store value from source register $S to a memory location pointed by
|
||||
// addressing register $D. Increment register $D.
|
||||
// addressing register $arD. Increment register $arD.
|
||||
void DSPEmitter::srri(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x3;
|
||||
|
|
@ -245,10 +244,10 @@ void DSPEmitter::srri(const UDSPInstruction opc)
|
|||
increment_addr_reg(dreg);
|
||||
}
|
||||
|
||||
// SRRN @$D, $S
|
||||
// SRRN @$arD, $S
|
||||
// 0001 1011 1dds ssss
|
||||
// Store value from source register $S to a memory location pointed by
|
||||
// addressing register $D. Add DSP_REG_IX0 register to register $D.
|
||||
// addressing register $arD. Add corresponding indexing register $ixD to register $arD.
|
||||
void DSPEmitter::srrn(const UDSPInstruction opc)
|
||||
{
|
||||
u8 dreg = (opc >> 5) & 0x3;
|
||||
|
|
|
|||
|
|
@ -130,8 +130,8 @@ void DSPEmitter::clrCompileSR(u16 bit)
|
|||
}
|
||||
// SBCLR #I
|
||||
// 0001 0011 aaaa aiii
|
||||
// bit of status register $sr. Bit number is calculated by adding 6 to
|
||||
// immediate value I.
|
||||
// Clear bit of status register $sr. Bit number is calculated by adding 6 to immediate value I;
|
||||
// thus, bits 6 through 13 (LZ through AM) can be cleared with this instruction.
|
||||
void DSPEmitter::sbclr(const UDSPInstruction opc)
|
||||
{
|
||||
u8 bit = (opc & 0x7) + 6;
|
||||
|
|
@ -141,8 +141,8 @@ void DSPEmitter::sbclr(const UDSPInstruction opc)
|
|||
|
||||
// SBSET #I
|
||||
// 0001 0010 aaaa aiii
|
||||
// Set bit of status register $sr. Bit number is calculated by adding 6 to
|
||||
// immediate value I.
|
||||
// Set bit of status register $sr. Bit number is calculated by adding 6 to immediate value I;
|
||||
// thus, bits 6 through 13 (LZ through AM) can be set with this instruction.
|
||||
void DSPEmitter::sbset(const UDSPInstruction opc)
|
||||
{
|
||||
u8 bit = (opc & 0x7) + 6;
|
||||
|
|
|
|||
|
|
@ -416,7 +416,7 @@ void DSPEmitter::mulx(const UDSPInstruction opc)
|
|||
}
|
||||
|
||||
// MULXAC $ax0.S, $ax1.T, $acR
|
||||
// 101s t01r xxxx xxxx
|
||||
// 101s t10r xxxx xxxx
|
||||
// Add product register to accumulator register $acR. Multiply one part
|
||||
// $ax0 by one part $ax1. Part is selected by S and
|
||||
// T bits. Zero selects low part, one selects high part.
|
||||
|
|
@ -487,7 +487,7 @@ void DSPEmitter::mulxmv(const UDSPInstruction opc)
|
|||
m_gpr.PutXReg(tmp1);
|
||||
}
|
||||
|
||||
// MULXMV $ax0.S, $ax1.T, $acR
|
||||
// MULXMVZ $ax0.S, $ax1.T, $acR
|
||||
// 101s t01r xxxx xxxx
|
||||
// Move product register to accumulator register $acR and clear (round) low part
|
||||
// of accumulator register $acR.l. Multiply one part $ax0 by one part $ax1
|
||||
|
|
@ -545,7 +545,7 @@ void DSPEmitter::mulc(const UDSPInstruction opc)
|
|||
}
|
||||
|
||||
// MULCAC $acS.m, $axT.h, $acR
|
||||
// 110s t10r xxxx xxxx
|
||||
// 110s t10r xxxx xxxx
|
||||
// Multiply mid part of accumulator register $acS.m by high part $axS.h of
|
||||
// secondary accumulator $axS (treat them both as signed). Add product
|
||||
// register before multiplication to accumulator $acR.
|
||||
|
|
@ -616,7 +616,7 @@ void DSPEmitter::mulcmv(const UDSPInstruction opc)
|
|||
}
|
||||
|
||||
// MULCMVZ $acS.m, $axT.h, $acR
|
||||
// 110s t01r xxxx xxxx
|
||||
// 110s t01r xxxx xxxx
|
||||
// Multiply mid part of accumulator register $acS.m by high part $axT.h of
|
||||
// secondary accumulator $axT (treat them both as signed). Move product
|
||||
// register before multiplication to accumulator $acR, set (round) low part of
|
||||
|
|
|
|||
Loading…
Reference in a new issue