From 8e902abca385dcd7e9c633ede01d318b19636970 Mon Sep 17 00:00:00 2001
From: degasus <wickmarkus@web.de>
Date: Sat, 14 May 2016 11:31:17 +0200
Subject: [PATCH] JitArm64: Implement DSI exception.

Ok, this falls back on all memory instructions, but it's a way to start.
---
 Source/Core/Core/PowerPC/JitArm64/Jit.cpp     | 25 +++++++++++++------
 .../PowerPC/JitArm64/JitArm64_LoadStore.cpp   |  7 ++++--
 .../JitArm64/JitArm64_LoadStoreFloating.cpp   |  2 ++
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
index 7cc24a9e7d..a8795bb4ed 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
@@ -6,6 +6,7 @@
 
 #include "Common/Arm64Emitter.h"
 #include "Common/CommonTypes.h"
+#include "Common/MathUtil.h"
 #include "Common/PerformanceCounter.h"
 #include "Common/StringUtil.h"
 #include "Common/Logging/Log.h"
@@ -590,12 +591,6 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
 				js.firstFPInstructionFound = true;
 			}
 
-			if (jo.memcheck && (opinfo->flags & FL_USE_FPU))
-			{
-				// Don't do this yet
-				BRK(0x7777);
-			}
-
 			JitArm64Tables::CompileInstruction(ops[i]);
 
 			// If we have a register that will never be used again, flush it.
@@ -604,8 +599,22 @@ const u8* JitArm64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer *code_buf, JitB
 
 			if (jo.memcheck && (opinfo->flags & FL_LOADSTORE))
 			{
-				// Don't do this yet
-				BRK(0x666);
+				ARM64Reg WA = gpr.GetReg();
+				LDR(INDEX_UNSIGNED, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
+				FixupBranch noException = TBZ(WA, IntLog2(EXCEPTION_DSI));
+
+				FixupBranch handleException = B();
+				SwitchToFarCode();
+				SetJumpTarget(handleException);
+
+				gpr.Flush(FLUSH_MAINTAIN_STATE);
+				fpr.Flush(FLUSH_MAINTAIN_STATE);
+
+				WriteExceptionExit(js.compilerPC);
+
+				SwitchToNearCode();
+				SetJumpTarget(noException);
+				gpr.Unlock(WA);
 			}
 		}
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
index 7bdb250c20..c4053ff779 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
@@ -375,6 +375,7 @@ void JitArm64::lXX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreOff);
+	FALLBACK_IF(jo.memcheck);
 
 	u32 a = inst.RA, b = inst.RB, d = inst.RD;
 	s32 offset = inst.SIMM_16;
@@ -480,6 +481,7 @@ void JitArm64::stX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreOff);
+	FALLBACK_IF(jo.memcheck);
 
 	u32 a = inst.RA, b = inst.RB, s = inst.RS;
 	s32 offset = inst.SIMM_16;
@@ -557,7 +559,7 @@ void JitArm64::lmw(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreOff);
-	FALLBACK_IF(!jo.fastmem);
+	FALLBACK_IF(!jo.fastmem || jo.memcheck);
 
 	u32 a = inst.RA;
 
@@ -643,7 +645,7 @@ void JitArm64::stmw(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreOff);
-	FALLBACK_IF(!jo.fastmem);
+	FALLBACK_IF(!jo.fastmem || jo.memcheck);
 
 	u32 a = inst.RA;
 
@@ -803,6 +805,7 @@ void JitArm64::dcbz(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreOff);
+	FALLBACK_IF(jo.memcheck);
 
 	int a = inst.RA, b = inst.RB;
 
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
index f27367f297..69ed5811d3 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp
@@ -23,6 +23,7 @@ void JitArm64::lfXX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreFloatingOff);
+	FALLBACK_IF(jo.memcheck);
 
 	u32 a = inst.RA, b = inst.RB;
 
@@ -210,6 +211,7 @@ void JitArm64::stfXX(UGeckoInstruction inst)
 {
 	INSTRUCTION_START
 	JITDISABLE(bJITLoadStoreFloatingOff);
+	FALLBACK_IF(jo.memcheck);
 
 	u32 a = inst.RA, b = inst.RB;