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Helps to add the new code to the repository.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6597 8ced0084-cf51-0410-be5f-012b33b47a6e
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skidau
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1 changed files with 296 additions and 0 deletions
296
Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
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Source/Core/DSPCore/Src/Jit/DSPJitLoadStore.cpp
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// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// Additional copyrights go to Duddie and Tratax (c) 2004
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#include "../DSPIntCCUtil.h"
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#include "../DSPIntUtil.h"
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#include "../DSPEmitter.h"
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#include "x64Emitter.h"
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#include "ABI.h"
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using namespace Gen;
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// SRS @M, $(0x18+S)
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// 0010 1sss mmmm mmmm
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// Move value from register $(0x18+D) to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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// Note: pc+=2 in duddie's doc seems wrong
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void DSPEmitter::srs(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x7) + 0x18;
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOVZX(32, 16, ECX, M(&g_dsp.r[reg]));
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MOV(32, R(EAX), M(&g_dsp.r[DSP_REG_CR]));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 16, RCX, MDisp(R11,reg*2));
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MOVZX(64, 8, RAX, MDisp(R11,DSP_REG_CR*2));
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#endif
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SHL(16, R(EAX), Imm8(8));
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OR(8, R(EAX), Imm8(opc & 0xFF));
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dmem_write();
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}
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// LRS $(0x18+D), @M
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// 0010 0ddd mmmm mmmm
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// Move value from data memory pointed by address CR[0-7] | M to register
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// $(0x18+D). That is, the upper 8 bits of the address are the bottom 8 bits
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// from CR, and the lower 8 bits are from the 8-bit immediate.
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void DSPEmitter::lrs(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x7) + 0x18;
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//u16 addr = (g_dsp.r[DSP_REG_CR] << 8) | (opc & 0xFF);
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#ifdef _M_IX86 // All32
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MOV(32, R(ECX), M(&g_dsp.r[DSP_REG_CR]));
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SHL(16, R(ECX), Imm8(8));
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OR(8, R(ECX), Imm8(opc & 0xFF));
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dmem_read();
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MOV(16, M(&g_dsp.r[reg]), R(EAX));
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#else
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOVZX(64, 8, RCX, MDisp(R11,DSP_REG_CR*2));
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SHL(16, R(ECX), Imm8(8));
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OR(8, R(ECX), Imm8(opc & 0xFF));
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dmem_read();
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MOV(64, R(R11), ImmPtr(g_dsp.r));
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MOV(16, MDisp(R11,reg*2), R(RAX));
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#endif
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dsp_conditional_extend_accum(reg);
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}
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// LR $D, @M
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// 0000 0000 110d dddd
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// mmmm mmmm mmmm mmmm
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// Move value from data memory pointed by address M to register $D.
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// FIXME: Perform additional operation depending on destination register.
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void DSPEmitter::lr(const UDSPInstruction opc)
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{
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int reg = opc & DSP_REG_MASK;
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u16 addr = dsp_imem_read(compilePC + 1);
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dmem_read_imm(addr);
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dsp_op_write_reg(reg, EAX);
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dsp_conditional_extend_accum(reg);
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}
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// SR @M, $S
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// 0000 0000 111s ssss
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// mmmm mmmm mmmm mmmm
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// Store value from register $S to a memory pointed by address M.
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// FIXME: Perform additional operation depending on destination register.
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void DSPEmitter::sr(const UDSPInstruction opc)
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{
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u8 reg = opc & DSP_REG_MASK;
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u16 addr = dsp_imem_read(compilePC + 1);
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dsp_op_read_reg(reg, ECX);
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dmem_write_imm(addr);
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}
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// SI @M, #I
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// 0001 0110 mmmm mmmm
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// iiii iiii iiii iiii
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// Store 16-bit immediate value I to a memory location pointed by address
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// M (M is 8-bit value sign extended).
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void DSPEmitter::si(const UDSPInstruction opc)
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{
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u16 addr = (s8)opc;
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u16 imm = dsp_imem_read(compilePC + 1);
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MOV(32, R(ECX), Imm32((u32)imm));
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dmem_write_imm(addr);
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}
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// LRR $D, @$S
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// 0001 1000 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrr(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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//}
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// LRRD $D, @$S
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// 0001 1000 1ssd dddd
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// Move value from data memory pointed by addressing register $S toregister $D.
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// Decrement register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrrd(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_decrement_addr_reg(sreg);
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//}
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// LRRI $D, @$S
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// 0001 1001 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Increment register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrri(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_increment_addr_reg(sreg);
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//}
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// LRRN $D, @$S
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// 0001 1001 1ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Add indexing register $(0x4+S) to register $S.
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// FIXME: Perform additional operation depending on destination register.
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//void DSPEmitter::lrrn(const UDSPInstruction opc)
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//{
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// u8 sreg = (opc >> 5) & 0x3;
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// u8 dreg = opc & 0x1f;
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// u16 val = dsp_dmem_read(dsp_op_read_reg(sreg));
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// dsp_op_write_reg(dreg, val);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[sreg] = dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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//}
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// SRR @$D, $S
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// 0001 1010 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srr(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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//}
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// SRRD @$D, $S
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// 0001 1010 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Decrement register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srrd(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_decrement_addr_reg(dreg);
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//}
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// SRRI @$D, $S
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// 0001 1011 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Increment register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srri(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_increment_addr_reg(dreg);
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//}
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// SRRN @$D, $S
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// 0001 1011 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Add DSP_REG_IX0 register to register $D.
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// FIXME: Perform additional operation depending on source register.
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//void DSPEmitter::srrn(const UDSPInstruction opc)
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//{
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// u8 dreg = (opc >> 5) & 0x3;
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// u8 sreg = opc & 0x1f;
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// u16 val = dsp_op_read_reg(sreg);
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// dsp_dmem_write(g_dsp.r[dreg], val);
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// g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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//}
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// ILRR $acD.m, @$arS
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// 0000 001d 0001 00ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m.
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//void DSPEmitter::ilrr(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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//}
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// ILRRD $acD.m, @$arS
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// 0000 001d 0001 01ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Decrement addressing register $arS.
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//void DSPEmitter::ilrrd(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_decrement_addr_reg(reg);
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//}
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// ILRRI $acD.m, @$S
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// 0000 001d 0001 10ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Increment addressing register $arS.
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//void DSPEmitter::ilrri(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_increment_addr_reg(reg);
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//}
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// ILRRN $acD.m, @$arS
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// 0000 001d 0001 11ss
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// Move value from instruction memory pointed by addressing register
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// $arS to mid accumulator register $acD.m. Add corresponding indexing
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// register $ixS to addressing register $arS.
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//void DSPEmitter::ilrrn(const UDSPInstruction opc)
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//{
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// u16 reg = opc & 0x3;
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// u16 dreg = DSP_REG_ACM0 + ((opc >> 8) & 1);
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// g_dsp.r[dreg] = dsp_imem_read(g_dsp.r[reg]);
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// dsp_conditional_extend_accum(dreg);
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// g_dsp.r[reg] = dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
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//}
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//} // namespace
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//
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