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https://github.com/dolphin-emu/dolphin.git
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Jit64: optionally accurate NaNs
When AccurateNaNs is enabled, NaNs are handled accurately by checking for NaN results and choosing the correct input NaN or replacing x86's generated -QNaN with +QNaN.
This commit is contained in:
Tillmann Karras
parent
881f6db2ab
commit
aec38466d9
7 changed files with 183 additions and 42 deletions
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@ -47,7 +47,7 @@ namespace BootManager
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// Apply fire liberally
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struct ConfigCache
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{
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bool valid, bCPUThread, bSkipIdle, bSyncGPUOnSkipIdleHack, bFPRF, bMMU, bDCBZOFF, m_EnableJIT, bDSPThread,
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bool valid, bCPUThread, bSkipIdle, bSyncGPUOnSkipIdleHack, bFPRF, bAccurateNaNs, bMMU, bDCBZOFF, m_EnableJIT, bDSPThread,
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bSyncGPU, bFastDiscSpeed, bDSPHLE, bHLE_BS2, bProgressive;
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int iCPUCore, Volume;
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int iWiimoteSource[MAX_BBMOTES];
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@ -106,6 +106,7 @@ bool BootCore(const std::string& _rFilename)
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config_cache.bSyncGPUOnSkipIdleHack = StartUp.bSyncGPUOnSkipIdleHack;
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config_cache.iCPUCore = StartUp.iCPUCore;
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config_cache.bFPRF = StartUp.bFPRF;
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config_cache.bAccurateNaNs = StartUp.bAccurateNaNs;
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config_cache.bMMU = StartUp.bMMU;
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config_cache.bDCBZOFF = StartUp.bDCBZOFF;
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config_cache.bSyncGPU = StartUp.bSyncGPU;
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@ -146,6 +147,7 @@ bool BootCore(const std::string& _rFilename)
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core_section->Get("SkipIdle", &StartUp.bSkipIdle, StartUp.bSkipIdle);
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core_section->Get("SyncOnSkipIdle", &StartUp.bSyncGPUOnSkipIdleHack, StartUp.bSyncGPUOnSkipIdleHack);
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core_section->Get("FPRF", &StartUp.bFPRF, StartUp.bFPRF);
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core_section->Get("AccurateNaNs", &StartUp.bAccurateNaNs, StartUp.bAccurateNaNs);
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core_section->Get("MMU", &StartUp.bMMU, StartUp.bMMU);
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core_section->Get("DCBZ", &StartUp.bDCBZOFF, StartUp.bDCBZOFF);
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core_section->Get("SyncGPU", &StartUp.bSyncGPU, StartUp.bSyncGPU);
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@ -273,6 +275,7 @@ void Stop()
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StartUp.bSyncGPUOnSkipIdleHack = config_cache.bSyncGPUOnSkipIdleHack;
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StartUp.iCPUCore = config_cache.iCPUCore;
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StartUp.bFPRF = config_cache.bFPRF;
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StartUp.bAccurateNaNs = config_cache.bAccurateNaNs;
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StartUp.bMMU = config_cache.bMMU;
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StartUp.bDCBZOFF = config_cache.bDCBZOFF;
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StartUp.bSyncGPU = config_cache.bSyncGPU;
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@ -33,7 +33,7 @@ SCoreStartupParameter::SCoreStartupParameter()
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bJITPairedOff(false), bJITSystemRegistersOff(false),
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bJITBranchOff(false),
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bJITILTimeProfiling(false), bJITILOutputIR(false),
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bFPRF(false),
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bFPRF(false), bAccurateNaNs(false),
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bCPUThread(true), bDSPThread(false), bDSPHLE(true),
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bSkipIdle(true), bSyncGPUOnSkipIdleHack(true), bNTSC(false), bForceNTSCJ(false),
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bHLE_BS2(true), bEnableCheats(false),
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@ -78,6 +78,7 @@ void SCoreStartupParameter::LoadDefaults()
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bDSPHLE = true;
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bFastmem = true;
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bFPRF = false;
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bAccurateNaNs = false;
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bMMU = false;
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bDCBZOFF = false;
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iBBDumpPort = -1;
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@ -163,6 +163,7 @@ struct SCoreStartupParameter
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bool bFastmem;
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bool bFPRF;
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bool bAccurateNaNs;
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bool bCPUThread;
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bool bDSPThread;
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@ -135,13 +135,18 @@ public:
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Gen::FixupBranch JumpIfCRFieldBit(int field, int bit, bool jump_if_set = true);
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void SetFPRFIfNeeded(Gen::X64Reg xmm);
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void HandleNaNs(UGeckoInstruction inst, Gen::X64Reg xmm_out, Gen::X64Reg xmm_in);
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void MultiplyImmediate(u32 imm, int a, int d, bool overflow);
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typedef u32 (*Operation)(u32 a, u32 b);
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void regimmop(int d, int a, bool binary, u32 value, Operation doop, void (Gen::XEmitter::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
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bool Rc = false, bool carry = false);
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void fp_tri_op(int d, int a, int b, bool reversible, bool single, void (Gen::XEmitter::*avxOp)(Gen::X64Reg, Gen::X64Reg, const Gen::OpArg&),
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void (Gen::XEmitter::*sseOp)(Gen::X64Reg, const Gen::OpArg&), bool packed = false, bool roundRHS = false);
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void regimmop(int d, int a, bool binary, u32 value, Operation doop,
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void (Gen::XEmitter::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
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bool Rc = false, bool carry = false);
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Gen::X64Reg fp_tri_op(int d, int a, int b, bool reversible, bool single,
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void (Gen::XEmitter::*avxOp)(Gen::X64Reg, Gen::X64Reg, const Gen::OpArg&),
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void (Gen::XEmitter::*sseOp)(Gen::X64Reg, const Gen::OpArg&),
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bool packed, bool preserve_inputs, bool roundRHS = false);
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void FloatCompare(UGeckoInstruction inst, bool upper = false);
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// OPCODES
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@ -138,6 +138,20 @@ public:
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LockX(args...);
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}
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template<typename T>
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void UnlockX(T x)
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{
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if (!xregs[x].locked)
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PanicAlert("RegCache: x %i already unlocked!", x);
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xregs[x].locked = false;
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}
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template<typename T, typename... Args>
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void UnlockX(T first, Args... args)
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{
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UnlockX(first);
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UnlockX(args...);
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}
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void UnlockAll();
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void UnlockAllX();
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@ -10,38 +10,37 @@
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using namespace Gen;
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static const u64 GC_ALIGNED16(psSignBits[2]) = {0x8000000000000000ULL, 0x0000000000000000ULL};
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static const u64 GC_ALIGNED16(psSignBits2[2]) = {0x8000000000000000ULL, 0x8000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask[2]) = {0x7FFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL};
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static const u64 GC_ALIGNED16(psAbsMask2[2]) = {0x7FFFFFFFFFFFFFFFULL, 0x7FFFFFFFFFFFFFFFULL};
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static const u64 GC_ALIGNED16(psSignBits[2]) = {0x8000000000000000ULL, 0x0000000000000000ULL};
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static const u64 GC_ALIGNED16(psSignBits2[2]) = {0x8000000000000000ULL, 0x8000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask[2]) = {0x7FFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL};
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static const u64 GC_ALIGNED16(psAbsMask2[2]) = {0x7FFFFFFFFFFFFFFFULL, 0x7FFFFFFFFFFFFFFFULL};
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static const u64 GC_ALIGNED16(psGeneratedQNaN[2]) = {0x7FF8000000000000ULL, 0x7FF8000000000000ULL};
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static const double GC_ALIGNED16(half_qnan_and_s32_max[2]) = {0x7FFFFFFF, -0x80000};
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void Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
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void (XEmitter::*sseOp)(X64Reg, const OpArg&), bool packed, bool roundRHS)
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X64Reg Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
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void (XEmitter::*sseOp)(X64Reg, const OpArg&), bool packed, bool preserve_inputs, bool roundRHS)
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{
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fpr.Lock(d, a, b);
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fpr.BindToRegister(d, d == a || d == b || !single);
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X64Reg dest = preserve_inputs ? XMM1 : fpr.RX(d);
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if (roundRHS)
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{
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if (d == a)
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if (d == a && !preserve_inputs)
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{
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Force25BitPrecision(XMM0, fpr.R(b), XMM1);
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(this->*sseOp)(fpr.RX(d), R(XMM0));
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}
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else
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{
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Force25BitPrecision(fpr.RX(d), fpr.R(b), XMM0);
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(this->*sseOp)(fpr.RX(d), fpr.R(a));
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Force25BitPrecision(dest, fpr.R(b), XMM0);
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(this->*sseOp)(dest, fpr.R(a));
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}
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}
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else
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{
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avx_op(avxOp, sseOp, fpr.RX(d), fpr.R(a), fpr.R(b), packed, reversible);
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avx_op(avxOp, sseOp, dest, fpr.R(a), fpr.R(b), packed, reversible);
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}
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if (single)
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ForceSinglePrecision(fpr.RX(d), fpr.R(d), packed, true);
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SetFPRFIfNeeded(fpr.RX(d));
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fpr.UnlockAll();
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return dest;
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}
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// We can avoid calculating FPRF if it's not needed; every float operation resets it, so
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@ -56,6 +55,112 @@ void Jit64::SetFPRFIfNeeded(X64Reg xmm)
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SetFPRF(xmm);
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}
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void Jit64::HandleNaNs(UGeckoInstruction inst, X64Reg xmm_out, X64Reg xmm)
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{
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// | PowerPC | x86
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// ---------------------+----------+---------
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// input NaN precedence | 1*3 + 2 | 1*2 + 3
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// generated QNaN | positive | negative
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//
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// Dragon Ball: Revenge of King Piccolo requires generated NaNs
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// to be positive, so we'll have to handle them manually.
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bAccurateNaNs)
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{
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if (xmm_out != xmm)
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MOVAPD(xmm_out, R(xmm));
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return;
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}
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_assert_(xmm != XMM0);
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std::vector<u32> inputs;
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u32 a = inst.FA, b = inst.FB, c = inst.FC;
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for (u32 i : {a, b, c})
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{
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if (!js.op->fregsIn[i])
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continue;
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if (std::find(inputs.begin(), inputs.end(), i) == inputs.end())
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inputs.push_back(i);
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}
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if (inst.OPCD != 4)
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{
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// not paired-single
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UCOMISD(xmm, R(xmm));
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FixupBranch handle_nan = J_CC(CC_P, true);
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SwitchToFarCode();
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SetJumpTarget(handle_nan);
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std::vector<FixupBranch> fixups;
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for (u32 x : inputs)
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{
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MOVDDUP(xmm, fpr.R(x));
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UCOMISD(xmm, R(xmm));
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fixups.push_back(J_CC(CC_P));
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}
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MOVDDUP(xmm, M(psGeneratedQNaN));
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for (FixupBranch fixup : fixups)
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SetJumpTarget(fixup);
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FixupBranch done = J(true);
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SwitchToNearCode();
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SetJumpTarget(done);
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}
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else
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{
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// paired-single
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std::reverse(inputs.begin(), inputs.end());
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if (cpu_info.bSSE4_1)
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{
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avx_op(&XEmitter::VCMPPD, &XEmitter::CMPPD, XMM0, R(xmm), R(xmm), CMP_UNORD);
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PTEST(XMM0, R(XMM0));
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FixupBranch handle_nan = J_CC(CC_NZ, true);
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SwitchToFarCode();
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SetJumpTarget(handle_nan);
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BLENDVPD(xmm, M(psGeneratedQNaN));
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for (u32 x : inputs)
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{
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avx_op(&XEmitter::VCMPPD, &XEmitter::CMPPD, XMM0, fpr.R(x), fpr.R(x), CMP_UNORD);
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BLENDVPD(xmm, fpr.R(x));
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}
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FixupBranch done = J(true);
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SwitchToNearCode();
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SetJumpTarget(done);
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}
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else
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{
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// SSE2 fallback
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X64Reg tmp = fpr.GetFreeXReg();
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fpr.FlushLockX(tmp);
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MOVAPD(XMM0, R(xmm));
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CMPPD(XMM0, R(XMM0), CMP_UNORD);
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MOVMSKPD(RSCRATCH, R(XMM0));
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TEST(32, R(RSCRATCH), R(RSCRATCH));
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FixupBranch handle_nan = J_CC(CC_NZ, true);
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SwitchToFarCode();
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SetJumpTarget(handle_nan);
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MOVAPD(tmp, R(XMM0));
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PANDN(XMM0, R(xmm));
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PAND(tmp, M(psGeneratedQNaN));
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POR(tmp, R(XMM0));
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MOVAPD(xmm, R(tmp));
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for (u32 x : inputs)
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{
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MOVAPD(XMM0, fpr.R(x));
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CMPPD(XMM0, R(XMM0), CMP_ORD);
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MOVAPD(tmp, R(XMM0));
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PANDN(XMM0, fpr.R(x));
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PAND(xmm, R(tmp));
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POR(xmm, R(XMM0));
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}
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FixupBranch done = J(true);
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SwitchToNearCode();
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SetJumpTarget(done);
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fpr.UnlockX(tmp);
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}
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}
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if (xmm_out != xmm)
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MOVAPD(xmm_out, R(xmm));
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}
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void Jit64::fp_arith(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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@ -80,20 +185,27 @@ void Jit64::fp_arith(UGeckoInstruction inst)
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packed = false;
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bool round_input = single && !jit->js.op->fprIsSingle[inst.FC];
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bool preserve_inputs = SConfig::GetInstance().m_LocalCoreStartupParameter.bAccurateNaNs;
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X64Reg dest = INVALID_REG;
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switch (inst.SUBOP5)
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{
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case 18: fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VDIVPD : &XEmitter::VDIVSD,
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packed ? &XEmitter::DIVPD : &XEmitter::DIVSD, packed); break;
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case 20: fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VSUBPD : &XEmitter::VSUBSD,
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packed ? &XEmitter::SUBPD : &XEmitter::SUBSD, packed); break;
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case 21: fp_tri_op(d, a, b, true, single, packed ? &XEmitter::VADDPD : &XEmitter::VADDSD,
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packed ? &XEmitter::ADDPD : &XEmitter::ADDSD, packed); break;
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case 25: fp_tri_op(d, a, c, true, single, packed ? &XEmitter::VMULPD : &XEmitter::VMULSD,
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packed ? &XEmitter::MULPD : &XEmitter::MULSD, packed, round_input); break;
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case 18: dest = fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VDIVPD : &XEmitter::VDIVSD,
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packed ? &XEmitter::DIVPD : &XEmitter::DIVSD, packed, preserve_inputs); break;
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case 20: dest = fp_tri_op(d, a, b, false, single, packed ? &XEmitter::VSUBPD : &XEmitter::VSUBSD,
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packed ? &XEmitter::SUBPD : &XEmitter::SUBSD, packed, preserve_inputs); break;
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case 21: dest = fp_tri_op(d, a, b, true, single, packed ? &XEmitter::VADDPD : &XEmitter::VADDSD,
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packed ? &XEmitter::ADDPD : &XEmitter::ADDSD, packed, preserve_inputs); break;
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case 25: dest = fp_tri_op(d, a, c, true, single, packed ? &XEmitter::VMULPD : &XEmitter::VMULSD,
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packed ? &XEmitter::MULPD : &XEmitter::MULSD, packed, preserve_inputs, round_input); break;
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default:
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_assert_msg_(DYNA_REC, 0, "fp_arith WTF!!!");
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}
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HandleNaNs(inst, fpr.RX(d), dest);
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if (single)
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ForceSinglePrecision(fpr.RX(d), fpr.R(d), packed, true);
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SetFPRFIfNeeded(fpr.RX(d));
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fpr.UnlockAll();
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}
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void Jit64::fmaddXX(UGeckoInstruction inst)
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@ -220,13 +332,17 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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if (inst.SUBOP5 == 31) //nmadd
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PXOR(XMM1, M(packed ? psSignBits2 : psSignBits));
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}
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fpr.BindToRegister(d, !single);
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if (single)
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ForceSinglePrecision(fpr.RX(d), R(XMM1), packed, true);
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{
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HandleNaNs(inst, fpr.RX(d), XMM1);
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ForceSinglePrecision(fpr.RX(d), fpr.R(d), packed, true);
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}
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else
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{
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HandleNaNs(inst, XMM1, XMM1);
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MOVSD(fpr.RX(d), R(XMM1));
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}
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SetFPRFIfNeeded(fpr.RX(d));
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fpr.UnlockAll();
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}
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@ -379,7 +495,6 @@ void Jit64::FloatCompare(UGeckoInstruction inst, bool upper)
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}
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else
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{
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// Are we masking sNaN invalid floating point exceptions? If not this could crash if we don't handle the exception?
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UCOMISD(fpr.RX(b), fpr.R(a));
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}
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@ -38,7 +38,7 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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fpr.Lock(a, b, c, d);
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OpArg op_a = fpr.R(a);
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fpr.BindToRegister(d, d == b || d == c);
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X64Reg tmp = XMM0;
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X64Reg tmp = XMM1;
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MOVDDUP(tmp, op_a); // {a.ps0, a.ps0}
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ADDPD(tmp, fpr.R(b)); // {a.ps0 + b.ps0, a.ps0 + b.ps1}
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switch (inst.SUBOP5)
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@ -55,9 +55,9 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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}
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else
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{
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MOVAPD(XMM1, fpr.R(c));
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SHUFPD(XMM1, R(tmp), 2);
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tmp = XMM1;
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MOVAPD(XMM0, fpr.R(c));
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SHUFPD(XMM0, R(tmp), 2);
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tmp = XMM0;
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}
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}
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else
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@ -68,7 +68,8 @@ void Jit64::ps_sum(UGeckoInstruction inst)
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default:
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PanicAlert("ps_sum WTF!!!");
|
||||
}
|
||||
ForceSinglePrecision(fpr.RX(d), R(tmp));
|
||||
HandleNaNs(inst, fpr.RX(d), tmp);
|
||||
ForceSinglePrecision(fpr.RX(d), fpr.R(d));
|
||||
SetFPRFIfNeeded(fpr.RX(d));
|
||||
fpr.UnlockAll();
|
||||
}
|
||||
|
|
@ -88,19 +89,20 @@ void Jit64::ps_muls(UGeckoInstruction inst)
|
|||
switch (inst.SUBOP5)
|
||||
{
|
||||
case 12: // ps_muls0
|
||||
MOVDDUP(XMM0, fpr.R(c));
|
||||
MOVDDUP(XMM1, fpr.R(c));
|
||||
break;
|
||||
case 13: // ps_muls1
|
||||
avx_op(&XEmitter::VSHUFPD, &XEmitter::SHUFPD, XMM0, fpr.R(c), fpr.R(c), 3);
|
||||
avx_op(&XEmitter::VSHUFPD, &XEmitter::SHUFPD, XMM1, fpr.R(c), fpr.R(c), 3);
|
||||
break;
|
||||
default:
|
||||
PanicAlert("ps_muls WTF!!!");
|
||||
}
|
||||
if (round_input)
|
||||
Force25BitPrecision(XMM0, R(XMM0), XMM1);
|
||||
MULPD(XMM0, fpr.R(a));
|
||||
Force25BitPrecision(XMM1, R(XMM1), XMM0);
|
||||
MULPD(XMM1, fpr.R(a));
|
||||
fpr.BindToRegister(d, false);
|
||||
ForceSinglePrecision(fpr.RX(d), R(XMM0));
|
||||
HandleNaNs(inst, fpr.RX(d), XMM1);
|
||||
ForceSinglePrecision(fpr.RX(d), fpr.R(d));
|
||||
SetFPRFIfNeeded(fpr.RX(d));
|
||||
fpr.UnlockAll();
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue