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IPC: Fix missing interrupt when writing to Y1/Y2

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The IPC interrupt is triggered when IY1/IY2 is set and Y1/Y2 is written
to even when this results in clearing the bit.

This shouldn't change anything in practice but it's a difference
that Dolphin wasn't taking into account, which made me waste some time
when I was writing a hwtest :/
This commit is contained in:
Léo Lam 2018-02-27 15:57:07 +01:00
parent 35e3775a77
commit b9f7d67667
1 changed files with 4 additions and 0 deletions
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4
Source/Core/Core/HW/WII_IPC.cpp
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@ -153,6 +153,10 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
mmio->Register(base | IPC_PPCCTRL, MMIO::ComplexRead<u32>([](u32) { return ctrl.ppc(); }),
MMIO::ComplexWrite<u32>([](u32, u32 val) {
ctrl.ppc(val);
// The IPC interrupt is triggered when IY1/IY2 is set and
// Y1/Y2 is written to -- even when this results in clearing the bit.
if ((val >> 2 & 1 && ctrl.IY1) || (val >> 1 & 1 && ctrl.IY2))
ppc_irq_flags |= INT_CAUSE_IPC_BROADWAY;
if (ctrl.X1)
HLE::GetIOS()->EnqueueIPCRequest(ppc_msg);
HLE::GetIOS()->UpdateIPC();