From ba1b624e1b3f8c21cafeb64a15fddd0059c6336a Mon Sep 17 00:00:00 2001
From: "Admiral H. Curtiss" <pikachu025@gmail.com>
Date: Mon, 9 Jan 2023 22:55:49 +0100
Subject: [PATCH] PowerPC: Remove MSR macro.

---
 Source/Core/Core/Boot/Boot.cpp                |  6 +-
 Source/Core/Core/Boot/Boot_BS2Emu.cpp         |  8 +--
 Source/Core/Core/CheatSearch.cpp              |  4 +-
 Source/Core/Core/FifoPlayer/FifoPlayer.cpp    |  2 +-
 Source/Core/Core/IOS/MIOS.cpp                 |  2 +-
 Source/Core/Core/PatchEngine.cpp              |  6 +-
 .../CachedInterpreter/CachedInterpreter.cpp   |  2 +-
 Source/Core/Core/PowerPC/GDBStub.cpp          |  4 +-
 .../Core/PowerPC/Interpreter/Interpreter.cpp  |  6 +-
 .../Interpreter/Interpreter_Branch.cpp        |  6 +-
 .../PowerPC/Interpreter/Interpreter_FPUtils.h |  2 +-
 .../Interpreter/Interpreter_LoadStore.cpp     | 18 +++---
 .../Interpreter_SystemRegisters.cpp           | 22 ++++----
 Source/Core/Core/PowerPC/Jit64/Jit.cpp        |  4 +-
 .../Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp |  6 +-
 .../PowerPC/Jit64/Jit_LoadStorePaired.cpp     |  4 +-
 .../Core/PowerPC/Jit64Common/EmuCodeBlock.cpp |  4 +-
 Source/Core/Core/PowerPC/JitArm64/Jit.cpp     |  4 +-
 .../PowerPC/JitArm64/JitArm64_LoadStore.cpp   |  4 +-
 .../JitArm64/JitArm64_LoadStorePaired.cpp     |  4 +-
 .../Core/Core/PowerPC/JitCommon/JitBase.cpp   |  3 +-
 .../Core/Core/PowerPC/JitCommon/JitCache.cpp  |  7 ++-
 Source/Core/Core/PowerPC/JitInterface.cpp     |  6 +-
 Source/Core/Core/PowerPC/MMU.cpp              | 45 +++++++--------
 Source/Core/Core/PowerPC/PowerPC.cpp          | 56 +++++++++----------
 Source/Core/Core/PowerPC/PowerPC.h            |  1 -
 26 files changed, 120 insertions(+), 116 deletions(-)

diff --git a/Source/Core/Core/Boot/Boot.cpp b/Source/Core/Core/Boot/Boot.cpp
index 9aa2e299e0..e2ce583404 100644
--- a/Source/Core/Core/Boot/Boot.cpp
+++ b/Source/Core/Core/Boot/Boot.cpp
@@ -462,9 +462,9 @@ bool CBoot::Load_BS2(Core::System& system, const std::string& boot_rom_filename)
   PowerPC::ppcState.gpr[4] = 0x00002030;
   PowerPC::ppcState.gpr[5] = 0x0000009c;
 
-  MSR.FP = 1;
-  MSR.DR = 1;
-  MSR.IR = 1;
+  PowerPC::ppcState.msr.FP = 1;
+  PowerPC::ppcState.msr.DR = 1;
+  PowerPC::ppcState.msr.IR = 1;
 
   PowerPC::ppcState.spr[SPR_HID0] = 0x0011c464;
   PowerPC::ppcState.spr[SPR_IBAT3U] = 0xfff0001f;
diff --git a/Source/Core/Core/Boot/Boot_BS2Emu.cpp b/Source/Core/Core/Boot/Boot_BS2Emu.cpp
index 7371512e04..02e02176a9 100644
--- a/Source/Core/Core/Boot/Boot_BS2Emu.cpp
+++ b/Source/Core/Core/Boot/Boot_BS2Emu.cpp
@@ -67,10 +67,10 @@ void CBoot::RunFunction(u32 address)
 void CBoot::SetupMSR()
 {
   // 0x0002032
-  MSR.RI = 1;
-  MSR.DR = 1;
-  MSR.IR = 1;
-  MSR.FP = 1;
+  PowerPC::ppcState.msr.RI = 1;
+  PowerPC::ppcState.msr.DR = 1;
+  PowerPC::ppcState.msr.IR = 1;
+  PowerPC::ppcState.msr.FP = 1;
 }
 
 void CBoot::SetupHID(bool is_wii)
diff --git a/Source/Core/Core/CheatSearch.cpp b/Source/Core/Core/CheatSearch.cpp
index 9d2d288555..3ad1a5c674 100644
--- a/Source/Core/Core/CheatSearch.cpp
+++ b/Source/Core/Core/CheatSearch.cpp
@@ -204,7 +204,7 @@ Cheats::NewSearch(const std::vector<Cheats::MemoryRange>& memory_ranges,
       return;
     }
 
-    if (address_space == PowerPC::RequestedAddressSpace::Virtual && !MSR.DR)
+    if (address_space == PowerPC::RequestedAddressSpace::Virtual && !PowerPC::ppcState.msr.DR)
     {
       error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible;
       return;
@@ -263,7 +263,7 @@ Cheats::NextSearch(const std::vector<Cheats::SearchResult<T>>& previous_results,
       return;
     }
 
-    if (address_space == PowerPC::RequestedAddressSpace::Virtual && !MSR.DR)
+    if (address_space == PowerPC::RequestedAddressSpace::Virtual && !PowerPC::ppcState.msr.DR)
     {
       error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible;
       return;
diff --git a/Source/Core/Core/FifoPlayer/FifoPlayer.cpp b/Source/Core/Core/FifoPlayer/FifoPlayer.cpp
index e85cc84cc6..4a61a5b886 100644
--- a/Source/Core/Core/FifoPlayer/FifoPlayer.cpp
+++ b/Source/Core/Core/FifoPlayer/FifoPlayer.cpp
@@ -632,7 +632,7 @@ void FifoPlayer::LoadMemory()
   UReg_MSR newMSR;
   newMSR.DR = 1;
   newMSR.IR = 1;
-  MSR.Hex = newMSR.Hex;
+  PowerPC::ppcState.msr.Hex = newMSR.Hex;
   PowerPC::ppcState.spr[SPR_IBAT0U] = 0x80001fff;
   PowerPC::ppcState.spr[SPR_IBAT0L] = 0x00000002;
   PowerPC::ppcState.spr[SPR_DBAT0U] = 0x80001fff;
diff --git a/Source/Core/Core/IOS/MIOS.cpp b/Source/Core/Core/IOS/MIOS.cpp
index 30d43a4e19..114fea242c 100644
--- a/Source/Core/Core/IOS/MIOS.cpp
+++ b/Source/Core/Core/IOS/MIOS.cpp
@@ -78,7 +78,7 @@ bool Load()
 
   const PowerPC::CoreMode core_mode = PowerPC::GetMode();
   PowerPC::SetMode(PowerPC::CoreMode::Interpreter);
-  MSR.Hex = 0;
+  PowerPC::ppcState.msr.Hex = 0;
   PowerPC::ppcState.pc = 0x3400;
   NOTICE_LOG_FMT(IOS, "Loaded MIOS and bootstrapped PPC.");
 
diff --git a/Source/Core/Core/PatchEngine.cpp b/Source/Core/Core/PatchEngine.cpp
index 8d313ec3d3..ce91f7d57f 100644
--- a/Source/Core/Core/PatchEngine.cpp
+++ b/Source/Core/Core/PatchEngine.cpp
@@ -277,7 +277,7 @@ static void ApplyMemoryPatches(std::span<const std::size_t> memory_patch_indices
 // We require at least 2 stack frames, if the stack is shallower than that then it won't work.
 static bool IsStackSane()
 {
-  DEBUG_ASSERT(MSR.DR && MSR.IR);
+  DEBUG_ASSERT(PowerPC::ppcState.msr.DR && PowerPC::ppcState.msr.IR);
 
   // Check the stack pointer
   u32 SP = GPR(1);
@@ -315,12 +315,12 @@ bool ApplyFramePatches()
   // callback hook we can end up catching the game in an exception vector.
   // We deal with this by returning false so that SystemTimers will reschedule us in a few cycles
   // where we can try again after the CPU hopefully returns back to the normal instruction flow.
-  if (!MSR.DR || !MSR.IR || !IsStackSane())
+  if (!PowerPC::ppcState.msr.DR || !PowerPC::ppcState.msr.IR || !IsStackSane())
   {
     DEBUG_LOG_FMT(ACTIONREPLAY,
                   "Need to retry later. CPU configuration is currently incorrect. PC = {:#010x}, "
                   "MSR = {:#010x}",
-                  PowerPC::ppcState.pc, MSR.Hex);
+                  PowerPC::ppcState.pc, PowerPC::ppcState.msr.Hex);
     return false;
   }
 
diff --git a/Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp b/Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
index edd874d4c6..1043e3bd38 100644
--- a/Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
+++ b/Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
@@ -164,7 +164,7 @@ static void WriteBrokenBlockNPC(UGeckoInstruction data)
 
 static bool CheckFPU(u32 data)
 {
-  if (!MSR.FP)
+  if (!PowerPC::ppcState.msr.FP)
   {
     PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE;
     PowerPC::CheckExceptions();
diff --git a/Source/Core/Core/PowerPC/GDBStub.cpp b/Source/Core/Core/PowerPC/GDBStub.cpp
index 9326570d4d..a38db8d159 100644
--- a/Source/Core/Core/PowerPC/GDBStub.cpp
+++ b/Source/Core/Core/PowerPC/GDBStub.cpp
@@ -432,7 +432,7 @@ static void ReadRegister()
       wbe32hex(reply, PowerPC::ppcState.pc);
       break;
     case 65:
-      wbe32hex(reply, MSR.Hex);
+      wbe32hex(reply, PowerPC::ppcState.msr.Hex);
       break;
     case 66:
       wbe32hex(reply, PowerPC::ppcState.cr.Get());
@@ -644,7 +644,7 @@ static void WriteRegister()
       PowerPC::ppcState.pc = re32hex(bufptr);
       break;
     case 65:
-      MSR.Hex = re32hex(bufptr);
+      PowerPC::ppcState.msr.Hex = re32hex(bufptr);
       break;
     case 66:
       PowerPC::ppcState.cr.Set(re32hex(bufptr));
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
index 2829dd211a..b9f17be7e9 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
@@ -132,8 +132,8 @@ static void Trace(const UGeckoInstruction& inst)
                 "INTER PC: {:08x} SRR0: {:08x} SRR1: {:08x} CRval: {:016x} "
                 "FPSCR: {:08x} MSR: {:08x} LR: {:08x} {} {:08x} {}",
                 PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.cr.fields[0],
-                PowerPC::ppcState.fpscr.Hex, MSR.Hex, PowerPC::ppcState.spr[8], regs, inst.hex,
-                ppc_inst);
+                PowerPC::ppcState.fpscr.Hex, PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8],
+                regs, inst.hex, ppc_inst);
 }
 
 bool Interpreter::HandleFunctionHooking(u32 address)
@@ -178,7 +178,7 @@ int Interpreter::SingleStepInner()
       GenerateProgramException(ProgramExceptionCause::IllegalInstruction);
       CheckExceptions();
     }
-    else if (MSR.FP)
+    else if (PowerPC::ppcState.msr.FP)
     {
       m_op_table[m_prev_inst.OPCD](m_prev_inst);
       if ((PowerPC::ppcState.Exceptions & EXCEPTION_DSI) != 0)
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp
index 2210e38e3b..c6a9155735 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp
@@ -100,7 +100,7 @@ void Interpreter::HLEFunction(UGeckoInstruction inst)
 
 void Interpreter::rfi(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -109,9 +109,9 @@ void Interpreter::rfi(UGeckoInstruction inst)
   // Restore saved bits from SRR1 to MSR.
   // Gecko/Broadway can save more bits than explicitly defined in ppc spec
   const u32 mask = 0x87C0FFFF;
-  MSR.Hex = (MSR.Hex & ~mask) | (SRR1 & mask);
+  PowerPC::ppcState.msr.Hex = (PowerPC::ppcState.msr.Hex & ~mask) | (SRR1 & mask);
   // MSR[13] is set to 0.
-  MSR.Hex &= 0xFFFBFFFF;
+  PowerPC::ppcState.msr.Hex &= 0xFFFBFFFF;
   // Here we should check if there are pending exceptions, and if their corresponding enable bits
   // are set
   // if above is true, we'd do:
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h b/Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h
index 94ebc65a83..0959c68162 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h
@@ -27,7 +27,7 @@ enum class FPCC
 
 inline void CheckFPExceptions(UReg_FPSCR fpscr)
 {
-  if (fpscr.FEX && (MSR.FE0 || MSR.FE1))
+  if (fpscr.FEX && (PowerPC::ppcState.msr.FE0 || PowerPC::ppcState.msr.FE1))
     GenerateProgramException(ProgramExceptionCause::FloatingPoint);
 }
 
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
index 3a02f61b03..555a9f4fb8 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
@@ -254,7 +254,7 @@ void Interpreter::lmw(UGeckoInstruction inst)
 {
   u32 address = Helper_Get_EA(PowerPC::ppcState, inst);
 
-  if ((address & 0b11) != 0 || MSR.LE)
+  if ((address & 0b11) != 0 || PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(address);
     return;
@@ -282,7 +282,7 @@ void Interpreter::stmw(UGeckoInstruction inst)
 {
   u32 address = Helper_Get_EA(PowerPC::ppcState, inst);
 
-  if ((address & 0b11) != 0 || MSR.LE)
+  if ((address & 0b11) != 0 || PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(address);
     return;
@@ -453,7 +453,7 @@ void Interpreter::dcbf(UGeckoInstruction inst)
 
 void Interpreter::dcbi(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -678,7 +678,7 @@ void Interpreter::lswx(UGeckoInstruction inst)
 {
   u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst);
 
-  if (MSR.LE)
+  if (PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(EA);
     return;
@@ -858,7 +858,7 @@ void Interpreter::lswi(UGeckoInstruction inst)
   if (inst.RA != 0)
     EA = rGPR[inst.RA];
 
-  if (MSR.LE)
+  if (PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(EA);
     return;
@@ -905,7 +905,7 @@ void Interpreter::stswi(UGeckoInstruction inst)
   if (inst.RA != 0)
     EA = rGPR[inst.RA];
 
-  if (MSR.LE)
+  if (PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(EA);
     return;
@@ -943,7 +943,7 @@ void Interpreter::stswx(UGeckoInstruction inst)
 {
   u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst);
 
-  if (MSR.LE)
+  if (PowerPC::ppcState.msr.LE)
   {
     GenerateAlignmentException(EA);
     return;
@@ -1051,7 +1051,7 @@ void Interpreter::sync(UGeckoInstruction inst)
 
 void Interpreter::tlbie(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -1065,7 +1065,7 @@ void Interpreter::tlbie(UGeckoInstruction inst)
 
 void Interpreter::tlbsync(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
   }
diff --git a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
index 074cb0390b..1a3c3fb102 100644
--- a/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
+++ b/Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
@@ -128,18 +128,18 @@ void Interpreter::mtcrf(UGeckoInstruction inst)
 
 void Interpreter::mfmsr(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
   }
 
-  rGPR[inst.RD] = MSR.Hex;
+  rGPR[inst.RD] = PowerPC::ppcState.msr.Hex;
 }
 
 void Interpreter::mfsr(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -150,7 +150,7 @@ void Interpreter::mfsr(UGeckoInstruction inst)
 
 void Interpreter::mfsrin(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -162,13 +162,13 @@ void Interpreter::mfsrin(UGeckoInstruction inst)
 
 void Interpreter::mtmsr(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
   }
 
-  MSR.Hex = rGPR[inst.RS];
+  PowerPC::ppcState.msr.Hex = rGPR[inst.RS];
 
   // FE0/FE1 may have been set
   CheckFPExceptions(PowerPC::ppcState.fpscr);
@@ -181,7 +181,7 @@ void Interpreter::mtmsr(UGeckoInstruction inst)
 
 void Interpreter::mtsr(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -194,7 +194,7 @@ void Interpreter::mtsr(UGeckoInstruction inst)
 
 void Interpreter::mtsrin(UGeckoInstruction inst)
 {
-  if (MSR.PR)
+  if (PowerPC::ppcState.msr.PR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -217,8 +217,8 @@ void Interpreter::mfspr(UGeckoInstruction inst)
   const u32 index = ((inst.SPR & 0x1F) << 5) + ((inst.SPR >> 5) & 0x1F);
 
   // XER, LR, CTR, and timebase halves are the only ones available in user mode.
-  if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR && index != SPR_TL &&
-      index != SPR_TU)
+  if (PowerPC::ppcState.msr.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR &&
+      index != SPR_TL && index != SPR_TU)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
@@ -288,7 +288,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
   const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
 
   // XER, LR, and CTR are the only ones available to be written to in user mode
-  if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR)
+  if (PowerPC::ppcState.msr.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR)
   {
     GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
     return;
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp
index 2e1e8d5706..7747f426c3 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp
@@ -758,8 +758,8 @@ void Jit64::Trace()
   DEBUG_LOG_FMT(DYNA_REC,
                 "JIT64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} "
                 "MSR: {:08x} LR: {:08x} {} {}",
-                PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, MSR.Hex,
-                PowerPC::ppcState.spr[8], regs, fregs);
+                PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex,
+                PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs);
 }
 
 void Jit64::Jit(u32 em_address)
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
index fe95271136..32e5207773 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
@@ -320,7 +320,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
   FixupBranch bat_lookup_failed;
   MOV(32, R(effective_address), R(addr));
   const u8* loop_start = GetCodePtr();
-  if (MSR.IR)
+  if (PowerPC::ppcState.msr.IR)
   {
     // Translate effective address to physical address.
     bat_lookup_failed = BATAddressLookup(addr, tmp, PowerPC::ibat_table.data());
@@ -349,7 +349,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
 
   SwitchToFarCode();
   SetJumpTarget(invalidate_needed);
-  if (MSR.IR)
+  if (PowerPC::ppcState.msr.IR)
     SetJumpTarget(bat_lookup_failed);
 
   BitSet32 registersInUse = CallerSavedRegistersInUse();
@@ -422,7 +422,7 @@ void Jit64::dcbz(UGeckoInstruction inst)
     end_dcbz_hack = J_CC(CC_L);
   }
 
-  bool emit_fast_path = MSR.DR && m_jit.jo.fastmem_arena;
+  bool emit_fast_path = PowerPC::ppcState.msr.DR && m_jit.jo.fastmem_arena;
 
   if (emit_fast_path)
   {
diff --git a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
index f2e608ca03..05d879784d 100644
--- a/Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
+++ b/Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
@@ -23,7 +23,7 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
   JITDISABLE(bJITLoadStorePairedOff);
 
   // For performance, the AsmCommon routines assume address translation is on.
-  FALLBACK_IF(!MSR.DR);
+  FALLBACK_IF(!PowerPC::ppcState.msr.DR);
 
   s32 offset = inst.SIMM_12;
   bool indexed = inst.OPCD == 4;
@@ -112,7 +112,7 @@ void Jit64::psq_lXX(UGeckoInstruction inst)
   JITDISABLE(bJITLoadStorePairedOff);
 
   // For performance, the AsmCommon routines assume address translation is on.
-  FALLBACK_IF(!MSR.DR);
+  FALLBACK_IF(!PowerPC::ppcState.msr.DR);
 
   s32 offset = inst.SIMM_12;
   bool indexed = inst.OPCD == 4;
diff --git a/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp b/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
index 3aefe52f7f..991b0cd7b1 100644
--- a/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
+++ b/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
@@ -367,7 +367,7 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress,
   }
 
   FixupBranch exit;
-  const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || MSR.DR;
+  const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || PowerPC::ppcState.msr.DR;
   const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
   if (fast_check_address)
   {
@@ -537,7 +537,7 @@ void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acces
   }
 
   FixupBranch exit;
-  const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || MSR.DR;
+  const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || PowerPC::ppcState.msr.DR;
   const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
   if (fast_check_address)
   {
diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
index 97467e5272..496b76ae01 100644
--- a/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/Jit.cpp
@@ -705,8 +705,8 @@ void JitArm64::Trace()
   DEBUG_LOG_FMT(DYNA_REC,
                 "JitArm64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} "
                 "MSR: {:08x} LR: {:08x} {} {}",
-                PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, MSR.Hex,
-                PowerPC::ppcState.spr[8], regs, fregs);
+                PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex,
+                PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs);
 }
 
 void JitArm64::Jit(u32 em_address)
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
index 64ba331b17..996b6e887f 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
@@ -731,7 +731,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
   // Translate effective address to physical address.
   const u8* loop_start = GetCodePtr();
   FixupBranch bat_lookup_failed;
-  if (MSR.IR)
+  if (PowerPC::ppcState.msr.IR)
   {
     bat_lookup_failed =
         BATAddressLookup(physical_addr, effective_addr, WA, PowerPC::ibat_table.data());
@@ -760,7 +760,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
 
   SwitchToFarCode();
   SetJumpTarget(invalidate_needed);
-  if (MSR.IR)
+  if (PowerPC::ppcState.msr.IR)
     SetJumpTarget(bat_lookup_failed);
 
   BitSet32 gprs_to_push = gpr.GetCallerSavedUsed();
diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
index a88543e995..45d0b50c01 100644
--- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
+++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
@@ -23,7 +23,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
   JITDISABLE(bJITLoadStorePairedOff);
 
   // If we have a fastmem arena, the asm routines assume address translation is on.
-  FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !MSR.DR);
+  FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !PowerPC::ppcState.msr.DR);
 
   // X30 is LR
   // X0 is the address
@@ -148,7 +148,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
   JITDISABLE(bJITLoadStorePairedOff);
 
   // If we have a fastmem arena, the asm routines assume address translation is on.
-  FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !MSR.DR);
+  FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !PowerPC::ppcState.msr.DR);
 
   // X30 is LR
   // X0 contains the scale
diff --git a/Source/Core/Core/PowerPC/JitCommon/JitBase.cpp b/Source/Core/Core/PowerPC/JitCommon/JitBase.cpp
index 27bdf3bb13..7b450f5d12 100644
--- a/Source/Core/Core/PowerPC/JitCommon/JitBase.cpp
+++ b/Source/Core/Core/PowerPC/JitCommon/JitBase.cpp
@@ -90,7 +90,8 @@ bool JitBase::CanMergeNextInstructions(int count) const
 void JitBase::UpdateMemoryAndExceptionOptions()
 {
   bool any_watchpoints = PowerPC::memchecks.HasAny();
-  jo.fastmem = m_fastmem_enabled && jo.fastmem_arena && (MSR.DR || !any_watchpoints);
+  jo.fastmem =
+      m_fastmem_enabled && jo.fastmem_arena && (PowerPC::ppcState.msr.DR || !any_watchpoints);
   jo.memcheck = m_mmu_enabled || m_pause_on_panic_enabled || any_watchpoints;
   jo.fp_exceptions = m_enable_float_exceptions;
   jo.div_by_zero_exceptions = m_enable_div_by_zero_exceptions;
diff --git a/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp b/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
index 8ee5f30caf..e4111e9096 100644
--- a/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
+++ b/Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
@@ -96,7 +96,7 @@ JitBlock* JitBaseBlockCache::AllocateBlock(u32 em_address)
   JitBlock& b = block_map.emplace(physical_address, JitBlock())->second;
   b.effectiveAddress = em_address;
   b.physicalAddress = physical_address;
-  b.msrBits = MSR.Hex & JIT_CACHE_MSR_MASK;
+  b.msrBits = PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK;
   b.linkData.clear();
   b.fast_block_map_index = 0;
   return &b;
@@ -171,9 +171,10 @@ const u8* JitBaseBlockCache::Dispatch()
   JitBlock* block = fast_block_map[FastLookupIndexForAddress(PowerPC::ppcState.pc)];
 
   if (!block || block->effectiveAddress != PowerPC::ppcState.pc ||
-      block->msrBits != (MSR.Hex & JIT_CACHE_MSR_MASK))
+      block->msrBits != (PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK))
   {
-    block = MoveBlockIntoFastCache(PowerPC::ppcState.pc, MSR.Hex & JIT_CACHE_MSR_MASK);
+    block = MoveBlockIntoFastCache(PowerPC::ppcState.pc,
+                                   PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK);
   }
 
   if (!block)
diff --git a/Source/Core/Core/PowerPC/JitInterface.cpp b/Source/Core/Core/PowerPC/JitInterface.cpp
index df6a5edae9..999cd43d81 100644
--- a/Source/Core/Core/PowerPC/JitInterface.cpp
+++ b/Source/Core/Core/PowerPC/JitInterface.cpp
@@ -153,12 +153,14 @@ std::variant<GetHostCodeError, GetHostCodeResult> GetHostCode(u32 address)
     return GetHostCodeError::NoJitActive;
   }
 
-  JitBlock* block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address, MSR.Hex);
+  JitBlock* block =
+      g_jit->GetBlockCache()->GetBlockFromStartAddress(address, PowerPC::ppcState.msr.Hex);
   if (!block)
   {
     for (int i = 0; i < 500; i++)
     {
-      block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address - 4 * i, MSR.Hex);
+      block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address - 4 * i,
+                                                               PowerPC::ppcState.msr.Hex);
       if (block)
         break;
     }
diff --git a/Source/Core/Core/PowerPC/MMU.cpp b/Source/Core/Core/PowerPC/MMU.cpp
index 8178206989..318b41ddac 100644
--- a/Source/Core/Core/PowerPC/MMU.cpp
+++ b/Source/Core/Core/PowerPC/MMU.cpp
@@ -191,7 +191,7 @@ static T ReadFromHardware(Memory::MemoryManager& memory, u32 em_address)
 
   bool wi = false;
 
-  if (!never_translate && MSR.DR)
+  if (!never_translate && PowerPC::ppcState.msr.DR)
   {
     auto translated_addr = TranslateAddress<flag>(em_address);
     if (!translated_addr.Success())
@@ -303,7 +303,7 @@ static void WriteToHardware(Core::System& system, Memory::MemoryManager& memory,
 
   bool wi = false;
 
-  if (!never_translate && MSR.DR)
+  if (!never_translate && PowerPC::ppcState.msr.DR)
   {
     auto translated_addr = TranslateAddress<flag>(em_address);
     if (!translated_addr.Success())
@@ -489,7 +489,7 @@ u32 Read_Opcode(u32 address)
 TryReadInstResult TryReadInstruction(u32 address)
 {
   bool from_bat = true;
-  if (MSR.IR)
+  if (PowerPC::ppcState.msr.IR)
   {
     auto tlb_addr = TranslateAddress<XCheckTLBFlag::Opcode>(address);
     if (!tlb_addr.Success())
@@ -540,7 +540,7 @@ std::optional<ReadResult<u32>> HostTryReadInstruction(const u32 address,
   case RequestedAddressSpace::Effective:
   {
     const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address);
-    return ReadResult<u32>(!!MSR.DR, value);
+    return ReadResult<u32>(!!PowerPC::ppcState.msr.DR, value);
   }
   case RequestedAddressSpace::Physical:
   {
@@ -550,7 +550,7 @@ std::optional<ReadResult<u32>> HostTryReadInstruction(const u32 address,
   }
   case RequestedAddressSpace::Virtual:
   {
-    if (!MSR.DR)
+    if (!PowerPC::ppcState.msr.DR)
       return std::nullopt;
     const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address);
     return ReadResult<u32>(true, value);
@@ -661,7 +661,7 @@ static std::optional<ReadResult<T>> HostTryReadUX(const u32 address, RequestedAd
   case RequestedAddressSpace::Effective:
   {
     T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address);
-    return ReadResult<T>(!!MSR.DR, std::move(value));
+    return ReadResult<T>(!!PowerPC::ppcState.msr.DR, std::move(value));
   }
   case RequestedAddressSpace::Physical:
   {
@@ -670,7 +670,7 @@ static std::optional<ReadResult<T>> HostTryReadUX(const u32 address, RequestedAd
   }
   case RequestedAddressSpace::Virtual:
   {
-    if (!MSR.DR)
+    if (!PowerPC::ppcState.msr.DR)
       return std::nullopt;
     T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address);
     return ReadResult<T>(true, std::move(value));
@@ -880,12 +880,12 @@ static std::optional<WriteResult> HostTryWriteUX(const u32 var, const u32 addres
   {
   case RequestedAddressSpace::Effective:
     WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size);
-    return WriteResult(!!MSR.DR);
+    return WriteResult(!!PowerPC::ppcState.msr.DR);
   case RequestedAddressSpace::Physical:
     WriteToHardware<XCheckTLBFlag::NoException, true>(system, memory, address, var, size);
     return WriteResult(false);
   case RequestedAddressSpace::Virtual:
-    if (!MSR.DR)
+    if (!PowerPC::ppcState.msr.DR)
       return std::nullopt;
     WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size);
     return WriteResult(true);
@@ -980,7 +980,7 @@ bool IsOptimizableRAMAddress(const u32 address)
   if (PowerPC::memchecks.HasAny())
     return false;
 
-  if (!MSR.DR)
+  if (!PowerPC::ppcState.msr.DR)
     return false;
 
   // TODO: This API needs to take an access size
@@ -1032,11 +1032,11 @@ bool HostIsRAMAddress(u32 address, RequestedAddressSpace space)
   switch (space)
   {
   case RequestedAddressSpace::Effective:
-    return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, MSR.DR);
+    return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, PowerPC::ppcState.msr.DR);
   case RequestedAddressSpace::Physical:
     return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, false);
   case RequestedAddressSpace::Virtual:
-    if (!MSR.DR)
+    if (!PowerPC::ppcState.msr.DR)
       return false;
     return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, true);
   }
@@ -1057,11 +1057,12 @@ bool HostIsInstructionRAMAddress(u32 address, RequestedAddressSpace space)
   switch (space)
   {
   case RequestedAddressSpace::Effective:
-    return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, MSR.IR);
+    return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address,
+                                                          PowerPC::ppcState.msr.IR);
   case RequestedAddressSpace::Physical:
     return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, false);
   case RequestedAddressSpace::Virtual:
-    if (!MSR.IR)
+    if (!PowerPC::ppcState.msr.IR)
       return false;
     return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, true);
   }
@@ -1151,7 +1152,7 @@ void DMA_MemoryToLC(const u32 cache_address, const u32 mem_address, const u32 nu
 void ClearDCacheLine(u32 address)
 {
   DEBUG_ASSERT((address & 0x1F) == 0);
-  if (MSR.DR)
+  if (PowerPC::ppcState.msr.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
     if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@@ -1183,7 +1184,7 @@ void StoreDCacheLine(u32 address)
 {
   address &= ~0x1F;
 
-  if (MSR.DR)
+  if (PowerPC::ppcState.msr.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
     if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@@ -1207,7 +1208,7 @@ void InvalidateDCacheLine(u32 address)
 {
   address &= ~0x1F;
 
-  if (MSR.DR)
+  if (PowerPC::ppcState.msr.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
     if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@@ -1229,7 +1230,7 @@ void FlushDCacheLine(u32 address)
 {
   address &= ~0x1F;
 
-  if (MSR.DR)
+  if (PowerPC::ppcState.msr.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
     if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@@ -1253,7 +1254,7 @@ void TouchDCacheLine(u32 address, bool store)
 {
   address &= ~0x1F;
 
-  if (MSR.DR)
+  if (PowerPC::ppcState.msr.DR)
   {
     auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
     if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@@ -1278,7 +1279,7 @@ u32 IsOptimizableMMIOAccess(u32 address, u32 access_size)
   if (PowerPC::memchecks.HasAny())
     return 0;
 
-  if (!MSR.DR)
+  if (!PowerPC::ppcState.msr.DR)
     return 0;
 
   // Translate address
@@ -1301,7 +1302,7 @@ bool IsOptimizableGatherPipeWrite(u32 address)
   if (PowerPC::memchecks.HasAny())
     return false;
 
-  if (!MSR.DR)
+  if (!PowerPC::ppcState.msr.DR)
     return false;
 
   // Translate address, only check BAT mapping.
@@ -1317,7 +1318,7 @@ bool IsOptimizableGatherPipeWrite(u32 address)
 
 TranslateResult JitCache_TranslateAddress(u32 address)
 {
-  if (!MSR.IR)
+  if (!PowerPC::ppcState.msr.IR)
     return TranslateResult{address};
 
   // TODO: We shouldn't use FLAG_OPCODE if the caller is the debugger.
diff --git a/Source/Core/Core/PowerPC/PowerPC.cpp b/Source/Core/Core/PowerPC/PowerPC.cpp
index b15109739a..aa6d4e951d 100644
--- a/Source/Core/Core/PowerPC/PowerPC.cpp
+++ b/Source/Core/Core/PowerPC/PowerPC.cpp
@@ -491,9 +491,9 @@ void CheckExceptions()
   {
     SRR0 = PowerPC::ppcState.npc;
     // Page fault occurred
-    SRR1 = (MSR.Hex & 0x87C0FFFF) | (1 << 30);
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 = (PowerPC::ppcState.msr.Hex & 0x87C0FFFF) | (1 << 30);
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000400;
 
     DEBUG_LOG_FMT(POWERPC, "EXCEPTION_ISI");
@@ -503,9 +503,9 @@ void CheckExceptions()
   {
     SRR0 = PowerPC::ppcState.pc;
     // SRR1 was partially set by GenerateProgramException, so bitwise or is used here
-    SRR1 |= MSR.Hex & 0x87C0FFFF;
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 |= PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000700;
 
     DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PROGRAM");
@@ -514,9 +514,9 @@ void CheckExceptions()
   else if (exceptions & EXCEPTION_SYSCALL)
   {
     SRR0 = PowerPC::ppcState.npc;
-    SRR1 = MSR.Hex & 0x87C0FFFF;
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000C00;
 
     DEBUG_LOG_FMT(POWERPC, "EXCEPTION_SYSCALL (PC={:08x})", PowerPC::ppcState.pc);
@@ -526,9 +526,9 @@ void CheckExceptions()
   {
     // This happens a lot - GameCube OS uses deferred FPU context switching
     SRR0 = PowerPC::ppcState.pc;  // re-execute the instruction
-    SRR1 = MSR.Hex & 0x87C0FFFF;
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000800;
 
     DEBUG_LOG_FMT(POWERPC, "EXCEPTION_FPU_UNAVAILABLE");
@@ -541,9 +541,9 @@ void CheckExceptions()
   else if (exceptions & EXCEPTION_DSI)
   {
     SRR0 = PowerPC::ppcState.pc;
-    SRR1 = MSR.Hex & 0x87C0FFFF;
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000300;
     // DSISR and DAR regs are changed in GenerateDSIException()
 
@@ -553,9 +553,9 @@ void CheckExceptions()
   else if (exceptions & EXCEPTION_ALIGNMENT)
   {
     SRR0 = PowerPC::ppcState.pc;
-    SRR1 = MSR.Hex & 0x87C0FFFF;
-    MSR.LE = MSR.ILE;
-    MSR.Hex &= ~0x04EF36;
+    SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+    PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+    PowerPC::ppcState.msr.Hex &= ~0x04EF36;
     PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000600;
 
     // TODO crazy amount of DSISR options to check out
@@ -577,15 +577,15 @@ void CheckExternalExceptions()
 
   // EXTERNAL INTERRUPT
   // Handling is delayed until MSR.EE=1.
-  if (exceptions && MSR.EE)
+  if (exceptions && PowerPC::ppcState.msr.EE)
   {
     if (exceptions & EXCEPTION_EXTERNAL_INT)
     {
       // Pokemon gets this "too early", it hasn't a handler yet
       SRR0 = PowerPC::ppcState.npc;
-      SRR1 = MSR.Hex & 0x87C0FFFF;
-      MSR.LE = MSR.ILE;
-      MSR.Hex &= ~0x04EF36;
+      SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+      PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+      PowerPC::ppcState.msr.Hex &= ~0x04EF36;
       PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000500;
 
       DEBUG_LOG_FMT(POWERPC, "EXCEPTION_EXTERNAL_INT");
@@ -596,9 +596,9 @@ void CheckExternalExceptions()
     else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
     {
       SRR0 = PowerPC::ppcState.npc;
-      SRR1 = MSR.Hex & 0x87C0FFFF;
-      MSR.LE = MSR.ILE;
-      MSR.Hex &= ~0x04EF36;
+      SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+      PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+      PowerPC::ppcState.msr.Hex &= ~0x04EF36;
       PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000F00;
 
       DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
@@ -607,9 +607,9 @@ void CheckExternalExceptions()
     else if (exceptions & EXCEPTION_DECREMENTER)
     {
       SRR0 = PowerPC::ppcState.npc;
-      SRR1 = MSR.Hex & 0x87C0FFFF;
-      MSR.LE = MSR.ILE;
-      MSR.Hex &= ~0x04EF36;
+      SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
+      PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
+      PowerPC::ppcState.msr.Hex &= ~0x04EF36;
       PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000900;
 
       DEBUG_LOG_FMT(POWERPC, "EXCEPTION_DECREMENTER");
diff --git a/Source/Core/Core/PowerPC/PowerPC.h b/Source/Core/Core/PowerPC/PowerPC.h
index 9bfff14299..17be96877c 100644
--- a/Source/Core/Core/PowerPC/PowerPC.h
+++ b/Source/Core/Core/PowerPC/PowerPC.h
@@ -245,7 +245,6 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
 #define THRM1(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM1])
 #define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2])
 #define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3])
-#define MSR PowerPC::ppcState.msr
 #define GPR(n) PowerPC::ppcState.gpr[n]
 
 #define rGPR PowerPC::ppcState.gpr