From 7f3c31d78de929244baadfb8719f1bf37b85296e Mon Sep 17 00:00:00 2001 From: Stenzek Date: Sat, 27 Jan 2018 18:12:54 +1000 Subject: [PATCH 1/3] Jit64: Set correct PC when emitting slowmem trampoline --- Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp | 1 + Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp b/Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp index 334fe8f7e1..118b6e553a 100644 --- a/Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp +++ b/Source/Core/Core/PowerPC/Jit64Common/Jit64Base.cpp @@ -70,6 +70,7 @@ bool Jitx86Base::BackPatch(u32 emAddress, SContext* ctx) js.generatingTrampoline = true; js.trampolineExceptionHandler = exceptionHandler; + js.compilerPC = info.pc; // Generate the trampoline. const u8* trampoline = trampolines.GenerateTrampoline(info); diff --git a/Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp b/Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp index bb9405daca..06cb42d881 100644 --- a/Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp +++ b/Source/Core/Core/PowerPC/Jit64Common/TrampolineCache.cpp @@ -63,9 +63,6 @@ const u8* TrampolineCache::GenerateWriteTrampoline(const TrampolineInfo& info) // Don't treat FIFO writes specially for now because they require a burst // check anyway. - // PC is used by memory watchpoints (if enabled) or to print accurate PC locations in debug logs - MOV(32, PPCSTATE(pc), Imm32(info.pc)); - SafeWriteRegToReg(info.op_arg, info.op_reg, info.accessSize << 3, info.offset, info.registersInUse, info.flags | SAFE_LOADSTORE_FORCE_SLOWMEM); From 8933fe599c5ae7127c6cd3de707eb73f3d79d117 Mon Sep 17 00:00:00 2001 From: Stenzek Date: Sat, 27 Jan 2018 18:21:11 +1000 Subject: [PATCH 2/3] Jit64: Update PC before slowmem reads as well as writes --- Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp b/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp index cdc91294a9..9c88cc8726 100644 --- a/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp +++ b/Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp @@ -376,6 +376,10 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress, exit = J(true); SetJumpTarget(slow); } + + // Helps external systems know which instruction triggered the read. + MOV(32, PPCSTATE(pc), Imm32(g_jit->js.compilerPC)); + size_t rsp_alignment = (flags & SAFE_LOADSTORE_NO_PROLOG) ? 8 : 0; ABI_PushRegistersAndAdjustStack(registersInUse, rsp_alignment); switch (accessSize) @@ -436,6 +440,9 @@ void EmuCodeBlock::SafeLoadToRegImmediate(X64Reg reg_value, u32 address, int acc return; } + // Helps external systems know which instruction triggered the read. + MOV(32, PPCSTATE(pc), Imm32(g_jit->js.compilerPC)); + // Fall back to general-case code. ABI_PushRegistersAndAdjustStack(registersInUse, 0); switch (accessSize) From 15efd42eba99558569a41e9088aba32371c8d99a Mon Sep 17 00:00:00 2001 From: Stenzek Date: Sat, 27 Jan 2018 22:32:57 +1000 Subject: [PATCH 3/3] Jit64: Don't flush PC in exception block These blocks can only be executed as a result of a DSI exception from a loadstore, where we now flush the PC register prior to the loadstore. --- Source/Core/Core/PowerPC/Jit64/Jit.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Source/Core/Core/PowerPC/Jit64/Jit.cpp b/Source/Core/Core/PowerPC/Jit64/Jit.cpp index facfe820e5..6b3ce7eda0 100644 --- a/Source/Core/Core/PowerPC/Jit64/Jit.cpp +++ b/Source/Core/Core/PowerPC/Jit64/Jit.cpp @@ -923,10 +923,6 @@ const u8* Jit64::DoJit(u32 em_address, PPCAnalyst::CodeBuffer* code_buf, JitBloc fprToFlush[js.revertFprLoad] = false; gpr.Flush(RegCache::FlushMode::MaintainState, gprToFlush); fpr.Flush(RegCache::FlushMode::MaintainState, fprToFlush); - - // If a memory exception occurs, the exception handler will read - // from PC. Update PC with the latest value in case that happens. - MOV(32, PPCSTATE(pc), Imm32(ops[i].address)); WriteExceptionExit(); SwitchToNearCode(); }