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https://github.com/dolphin-emu/dolphin.git
synced 2024-09-20 19:31:53 +02:00
some docs small clean up fixed the loop size correctly I hope this time
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2893 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
nakeee
parent
956b06700d
commit
5f5b43c659
3 changed files with 137 additions and 50 deletions
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@ -145,7 +145,8 @@ void loop(const UDSPInstruction& opc)
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g_dsp.pc = loop_pc;
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}
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g_dsp.pc = loop_pc + opSize[dsp_peek_code()];
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// g_dsp.pc = loop_pc;
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g_dsp.pc =+ opSize[dsp_peek_code()];
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}
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void loopi(const UDSPInstruction& opc)
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@ -159,7 +160,8 @@ void loopi(const UDSPInstruction& opc)
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g_dsp.pc = loop_pc;
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}
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g_dsp.pc = loop_pc + opSize[dsp_peek_code()];
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// g_dsp.pc = loop_pc;
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g_dsp.pc =+ opSize[dsp_peek_code()];
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}
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void bloop(const UDSPInstruction& opc)
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@ -176,7 +178,8 @@ void bloop(const UDSPInstruction& opc)
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}
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else
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{
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g_dsp.pc = loop_pc + opSize[dsp_peek_code()];
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g_dsp.pc = loop_pc;
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g_dsp.pc =+ opSize[dsp_peek_code()];
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}
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}
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@ -193,7 +196,8 @@ void bloopi(const UDSPInstruction& opc)
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}
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else
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{
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g_dsp.pc = loop_pc + opSize[dsp_peek_code()];
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g_dsp.pc = loop_pc;
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g_dsp.pc =+ opSize[dsp_peek_code()];
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}
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}
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@ -208,6 +212,10 @@ void mrr(const UDSPInstruction& opc)
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dsp_op_write_reg(dreg, val);
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}
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// LRR $D, @$S
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// 0001 1000 0ssd dddd
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// Move value from data memory pointed by addressing register $S toregister $D.
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// FIXME: Perform additional operation depending on destination register.
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void lrr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 5) & 0x3;
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@ -215,27 +223,59 @@ void lrr(const UDSPInstruction& opc)
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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// post processing of source reg
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switch ((opc.hex >> 7) & 0x3)
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{
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case 0x0: // LRR
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break;
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case 0x1: // LRRD
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g_dsp.r[sreg]--;
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break;
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case 0x2: // LRRI
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g_dsp.r[sreg]++;
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break;
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case 0x3: // LRRN
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g_dsp.r[sreg] += g_dsp.r[sreg + 4];
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break;
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}
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}
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// LRRD $D, @$S
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// 0001 1000 1ssd dddd
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// Move value from data memory pointed by addressing register $S toregister $D.
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// Decrement register $S.
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// FIXME: Perform additional operation depending on destination register.
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void lrrd(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 5) & 0x3;
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u8 dreg = opc.hex & 0x1f;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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g_dsp.r[sreg]--;
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}
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// LRRI $D, @$S
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// 0001 1001 0ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Increment register $S.
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// FIXME: Perform additional operation depending on destination register.
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void lrri(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 5) & 0x3;
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u8 dreg = opc.hex & 0x1f;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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g_dsp.r[sreg]++;
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}
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// LRRN $D, @$S
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// 0001 1001 1ssd dddd
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// Move value from data memory pointed by addressing register $S to register $D.
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// Add indexing register $(0x4+S) to register $S.
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// FIXME: Perform additional operation depending on destination register.
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void lrrn(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 5) & 0x3;
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u8 dreg = opc.hex & 0x1f;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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g_dsp.r[sreg] += g_dsp.r[sreg + 4];
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}
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// SRR @$D, $S
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// 0001 1010 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D.
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// FIXME: Perform additional operation depending on source register.
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void srr(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x3;
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@ -243,25 +283,51 @@ void srr(const UDSPInstruction& opc)
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u16 val = dsp_op_read_reg(sreg);
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dsp_dmem_write(g_dsp.r[dreg], val);
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}
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// SRRD @$D, $S
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// 0001 1010 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Decrement register $D.
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// FIXME: Perform additional operation depending on source register.
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void srrd(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x3;
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u8 sreg = opc.hex & 0x1f;
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// post processing of dest reg
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switch ((opc.hex >> 7) & 0x3)
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{
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case 0x0: // SRR
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break;
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u16 val = dsp_op_read_reg(sreg);
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dsp_dmem_write(g_dsp.r[dreg], val);
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g_dsp.r[dreg]--;
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}
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case 0x1: // SRRD
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g_dsp.r[dreg]--;
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break;
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// SRRI @$D, $S
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// 0001 1011 0dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Increment register $D.
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// FIXME: Perform additional operation depending on source register.
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void srri(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x3;
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u8 sreg = opc.hex & 0x1f;
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case 0x2: // SRRI
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g_dsp.r[dreg]++;
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break;
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u16 val = dsp_op_read_reg(sreg);
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dsp_dmem_write(g_dsp.r[dreg], val);
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g_dsp.r[dreg]++;
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}
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case 0x3: // SRRX
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g_dsp.r[dreg] += g_dsp.r[dreg + 4];
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break;
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}
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// SRRN @$D, $S
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// 0001 1011 1dds ssss
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// Store value from source register $S to a memory location pointed by
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// addressing register $D. Add indexing register $(0x4+D) to register $D.
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// FIXME: Perform additional operation depending on source register.
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void srrn(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x3;
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u8 sreg = opc.hex & 0x1f;
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u16 val = dsp_op_read_reg(sreg);
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dsp_dmem_write(g_dsp.r[dreg], val);
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g_dsp.r[dreg] += g_dsp.r[dreg + 4];
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}
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// FIXME inside
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@ -1354,13 +1420,25 @@ void msubc(const UDSPInstruction& opc)
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dsp_set_long_prod(prod);
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}
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// SRS @M, $(0x18+S)
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// 0010 1sss mmmm mmmm
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// Store value from register $(0x18+S) to a memory pointed by address M.
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// (8-bit sign extended).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in doddie's doc seems wrong
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void srs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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u16 addr = (s8)opc.hex;
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dsp_dmem_write(addr, g_dsp.r[reg]);
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dsp_dmem_write(addr, g_dsp.r[reg]);
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}
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// LRS $(0x18+D), @M
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// 0010 0ddd mmmm mmmm
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// Move value from data memory pointed by address M (8-bit sign
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// extended) to register $(0x18+D).
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// FIXME: Perform additional operation depending on destination register.
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// Note: pc+=2 in doddie's doc seems wrong
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void lrs(const UDSPInstruction& opc)
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{
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u8 reg = ((opc.hex >> 8) & 0x7) + 0x18;
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@ -41,7 +41,13 @@ void bloop(const UDSPInstruction& opc);
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void bloopi(const UDSPInstruction& opc);
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void mrr(const UDSPInstruction& opc);
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void lrr(const UDSPInstruction& opc);
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void lrrd(const UDSPInstruction& opc);
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void lrri(const UDSPInstruction& opc);
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void lrrn(const UDSPInstruction& opc);
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void srr(const UDSPInstruction& opc);
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void srrd(const UDSPInstruction& opc);
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void srri(const UDSPInstruction& opc);
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void srrn(const UDSPInstruction& opc);
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void lri(const UDSPInstruction& opc);
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void lris(const UDSPInstruction& opc);
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void lr(const UDSPInstruction& opc);
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@ -185,21 +185,24 @@ DSPOPCTemplate opcodes[] =
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{"ILRRI", 0x0218, 0xfedc, DSPInterpreter::ilrr, nop, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, NULL, NULL},
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// load and store value pointed by indexing reg and increment; LRR/SRR variants
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{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"LRR", 0x1800, 0xff80, DSPInterpreter::lrr, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"LRRD", 0x1880, 0xff80, DSPInterpreter::lrrd, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"LRRI", 0x1900, 0xff80, DSPInterpreter::lrri, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"LRRN", 0x1980, 0xff80, DSPInterpreter::lrrn, nop, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, NULL, NULL},
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{"SRR", 0x1a00, 0xff80, DSPInterpreter::srr, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRRD", 0x1a80, 0xff80, DSPInterpreter::srrd, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRRI", 0x1b00, 0xff80, DSPInterpreter::srri, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"SRRN", 0x1b80, 0xff80, DSPInterpreter::srrn, nop, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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// LOOPS
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{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"LOOPI", 0x1000, 0xff00, DSPInterpreter::loopi, nop, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, NULL, NULL},
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{"BLOOPI", 0x1100, 0xff00, DSPInterpreter::bloopi, nop, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"LOOP", 0x0040, 0xffe0, DSPInterpreter::loop, nop, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, NULL, NULL},
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{"BLOOP", 0x0060, 0xffe0, DSPInterpreter::bloop, nop, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_VAL, 2, 1, 0, 0xffff}}, NULL, NULL},
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{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL},
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{"ADDARN", 0x0010, 0xfff0, DSPInterpreter::addarn, nop, 2, 2, {{P_REG, 1, 0, 0, 0x00c0}, {P_REG, 2, 1, 0, 0x0003}}, NULL, NULL},
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// opcodes that can be extended
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// extended opcodes, note size of opcode will be set to 0
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