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PowerPC: Remove MSR macro.

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This commit is contained in:
Admiral H. Curtiss 2023-01-09 22:55:49 +01:00
parent 4b6b8fa1ae
commit ba1b624e1b
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GPG key ID: F051B4C4044F33FB
26 changed files with 120 additions and 116 deletions
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6
Source/Core/Core/Boot/Boot.cpp
View file

@ -462,9 +462,9 @@ bool CBoot::Load_BS2(Core::System& system, const std::string& boot_rom_filename)
PowerPC::ppcState.gpr[4] = 0x00002030; PowerPC::ppcState.gpr[4] = 0x00002030;
PowerPC::ppcState.gpr[5] = 0x0000009c; PowerPC::ppcState.gpr[5] = 0x0000009c;
MSR.FP = 1; PowerPC::ppcState.msr.FP = 1;
MSR.DR = 1; PowerPC::ppcState.msr.DR = 1;
MSR.IR = 1; PowerPC::ppcState.msr.IR = 1;
PowerPC::ppcState.spr[SPR_HID0] = 0x0011c464; PowerPC::ppcState.spr[SPR_HID0] = 0x0011c464;
PowerPC::ppcState.spr[SPR_IBAT3U] = 0xfff0001f; PowerPC::ppcState.spr[SPR_IBAT3U] = 0xfff0001f;

8
Source/Core/Core/Boot/Boot_BS2Emu.cpp
View file

@ -67,10 +67,10 @@ void CBoot::RunFunction(u32 address)
void CBoot::SetupMSR() void CBoot::SetupMSR()
{ {
// 0x0002032 // 0x0002032
MSR.RI = 1; PowerPC::ppcState.msr.RI = 1;
MSR.DR = 1; PowerPC::ppcState.msr.DR = 1;
MSR.IR = 1; PowerPC::ppcState.msr.IR = 1;
MSR.FP = 1; PowerPC::ppcState.msr.FP = 1;
} }
void CBoot::SetupHID(bool is_wii) void CBoot::SetupHID(bool is_wii)

4
Source/Core/Core/CheatSearch.cpp
View file

@ -204,7 +204,7 @@ Cheats::NewSearch(const std::vector<Cheats::MemoryRange>& memory_ranges,
return; return;
} }
if (address_space == PowerPC::RequestedAddressSpace::Virtual && !MSR.DR) if (address_space == PowerPC::RequestedAddressSpace::Virtual && !PowerPC::ppcState.msr.DR)
{ {
error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible; error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible;
return; return;
@ -263,7 +263,7 @@ Cheats::NextSearch(const std::vector<Cheats::SearchResult<T>>& previous_results,
return; return;
} }
if (address_space == PowerPC::RequestedAddressSpace::Virtual && !MSR.DR) if (address_space == PowerPC::RequestedAddressSpace::Virtual && !PowerPC::ppcState.msr.DR)
{ {
error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible; error_code = Cheats::SearchErrorCode::VirtualAddressesCurrentlyNotAccessible;
return; return;

2
Source/Core/Core/FifoPlayer/FifoPlayer.cpp
View file

@ -632,7 +632,7 @@ void FifoPlayer::LoadMemory()
UReg_MSR newMSR; UReg_MSR newMSR;
newMSR.DR = 1; newMSR.DR = 1;
newMSR.IR = 1; newMSR.IR = 1;
MSR.Hex = newMSR.Hex; PowerPC::ppcState.msr.Hex = newMSR.Hex;
PowerPC::ppcState.spr[SPR_IBAT0U] = 0x80001fff; PowerPC::ppcState.spr[SPR_IBAT0U] = 0x80001fff;
PowerPC::ppcState.spr[SPR_IBAT0L] = 0x00000002; PowerPC::ppcState.spr[SPR_IBAT0L] = 0x00000002;
PowerPC::ppcState.spr[SPR_DBAT0U] = 0x80001fff; PowerPC::ppcState.spr[SPR_DBAT0U] = 0x80001fff;

2
Source/Core/Core/IOS/MIOS.cpp
View file

@ -78,7 +78,7 @@ bool Load()
const PowerPC::CoreMode core_mode = PowerPC::GetMode(); const PowerPC::CoreMode core_mode = PowerPC::GetMode();
PowerPC::SetMode(PowerPC::CoreMode::Interpreter); PowerPC::SetMode(PowerPC::CoreMode::Interpreter);
MSR.Hex = 0; PowerPC::ppcState.msr.Hex = 0;
PowerPC::ppcState.pc = 0x3400; PowerPC::ppcState.pc = 0x3400;
NOTICE_LOG_FMT(IOS, "Loaded MIOS and bootstrapped PPC."); NOTICE_LOG_FMT(IOS, "Loaded MIOS and bootstrapped PPC.");

6
Source/Core/Core/PatchEngine.cpp
View file

@ -277,7 +277,7 @@ static void ApplyMemoryPatches(std::span<const std::size_t> memory_patch_indices
// We require at least 2 stack frames, if the stack is shallower than that then it won't work. // We require at least 2 stack frames, if the stack is shallower than that then it won't work.
static bool IsStackSane() static bool IsStackSane()
{ {
DEBUG_ASSERT(MSR.DR && MSR.IR); DEBUG_ASSERT(PowerPC::ppcState.msr.DR && PowerPC::ppcState.msr.IR);
// Check the stack pointer // Check the stack pointer
u32 SP = GPR(1); u32 SP = GPR(1);
@ -315,12 +315,12 @@ bool ApplyFramePatches()
// callback hook we can end up catching the game in an exception vector. // callback hook we can end up catching the game in an exception vector.
// We deal with this by returning false so that SystemTimers will reschedule us in a few cycles // We deal with this by returning false so that SystemTimers will reschedule us in a few cycles
// where we can try again after the CPU hopefully returns back to the normal instruction flow. // where we can try again after the CPU hopefully returns back to the normal instruction flow.
if (!MSR.DR || !MSR.IR || !IsStackSane()) if (!PowerPC::ppcState.msr.DR || !PowerPC::ppcState.msr.IR || !IsStackSane())
{ {
DEBUG_LOG_FMT(ACTIONREPLAY, DEBUG_LOG_FMT(ACTIONREPLAY,
"Need to retry later. CPU configuration is currently incorrect. PC = {:#010x}, " "Need to retry later. CPU configuration is currently incorrect. PC = {:#010x}, "
"MSR = {:#010x}", "MSR = {:#010x}",
PowerPC::ppcState.pc, MSR.Hex); PowerPC::ppcState.pc, PowerPC::ppcState.msr.Hex);
return false; return false;
} }

2
Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
View file

@ -164,7 +164,7 @@ static void WriteBrokenBlockNPC(UGeckoInstruction data)
static bool CheckFPU(u32 data) static bool CheckFPU(u32 data)
{ {
if (!MSR.FP) if (!PowerPC::ppcState.msr.FP)
{ {
PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE; PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE;
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();

4
Source/Core/Core/PowerPC/GDBStub.cpp
View file

@ -432,7 +432,7 @@ static void ReadRegister()
wbe32hex(reply, PowerPC::ppcState.pc); wbe32hex(reply, PowerPC::ppcState.pc);
break; break;
case 65: case 65:
wbe32hex(reply, MSR.Hex); wbe32hex(reply, PowerPC::ppcState.msr.Hex);
break; break;
case 66: case 66:
wbe32hex(reply, PowerPC::ppcState.cr.Get()); wbe32hex(reply, PowerPC::ppcState.cr.Get());
@ -644,7 +644,7 @@ static void WriteRegister()
PowerPC::ppcState.pc = re32hex(bufptr); PowerPC::ppcState.pc = re32hex(bufptr);
break; break;
case 65: case 65:
MSR.Hex = re32hex(bufptr); PowerPC::ppcState.msr.Hex = re32hex(bufptr);
break; break;
case 66: case 66:
PowerPC::ppcState.cr.Set(re32hex(bufptr)); PowerPC::ppcState.cr.Set(re32hex(bufptr));

6
Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
View file

@ -132,8 +132,8 @@ static void Trace(const UGeckoInstruction& inst)
"INTER PC: {:08x} SRR0: {:08x} SRR1: {:08x} CRval: {:016x} " "INTER PC: {:08x} SRR0: {:08x} SRR1: {:08x} CRval: {:016x} "
"FPSCR: {:08x} MSR: {:08x} LR: {:08x} {} {:08x} {}", "FPSCR: {:08x} MSR: {:08x} LR: {:08x} {} {:08x} {}",
PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.cr.fields[0], PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.cr.fields[0],
PowerPC::ppcState.fpscr.Hex, MSR.Hex, PowerPC::ppcState.spr[8], regs, inst.hex, PowerPC::ppcState.fpscr.Hex, PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8],
ppc_inst); regs, inst.hex, ppc_inst);
} }
bool Interpreter::HandleFunctionHooking(u32 address) bool Interpreter::HandleFunctionHooking(u32 address)
@ -178,7 +178,7 @@ int Interpreter::SingleStepInner()
GenerateProgramException(ProgramExceptionCause::IllegalInstruction); GenerateProgramException(ProgramExceptionCause::IllegalInstruction);
CheckExceptions(); CheckExceptions();
} }
else if (MSR.FP) else if (PowerPC::ppcState.msr.FP)
{ {
m_op_table[m_prev_inst.OPCD](m_prev_inst); m_op_table[m_prev_inst.OPCD](m_prev_inst);
if ((PowerPC::ppcState.Exceptions & EXCEPTION_DSI) != 0) if ((PowerPC::ppcState.Exceptions & EXCEPTION_DSI) != 0)

6
Source/Core/Core/PowerPC/Interpreter/Interpreter_Branch.cpp
View file

@ -100,7 +100,7 @@ void Interpreter::HLEFunction(UGeckoInstruction inst)
void Interpreter::rfi(UGeckoInstruction inst) void Interpreter::rfi(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -109,9 +109,9 @@ void Interpreter::rfi(UGeckoInstruction inst)
// Restore saved bits from SRR1 to MSR. // Restore saved bits from SRR1 to MSR.
// Gecko/Broadway can save more bits than explicitly defined in ppc spec // Gecko/Broadway can save more bits than explicitly defined in ppc spec
const u32 mask = 0x87C0FFFF; const u32 mask = 0x87C0FFFF;
MSR.Hex = (MSR.Hex & ~mask) | (SRR1 & mask); PowerPC::ppcState.msr.Hex = (PowerPC::ppcState.msr.Hex & ~mask) | (SRR1 & mask);
// MSR[13] is set to 0. // MSR[13] is set to 0.
MSR.Hex &= 0xFFFBFFFF; PowerPC::ppcState.msr.Hex &= 0xFFFBFFFF;
// Here we should check if there are pending exceptions, and if their corresponding enable bits // Here we should check if there are pending exceptions, and if their corresponding enable bits
// are set // are set
// if above is true, we'd do: // if above is true, we'd do:

2
Source/Core/Core/PowerPC/Interpreter/Interpreter_FPUtils.h
View file

@ -27,7 +27,7 @@ enum class FPCC
inline void CheckFPExceptions(UReg_FPSCR fpscr) inline void CheckFPExceptions(UReg_FPSCR fpscr)
{ {
if (fpscr.FEX && (MSR.FE0 || MSR.FE1)) if (fpscr.FEX && (PowerPC::ppcState.msr.FE0 || PowerPC::ppcState.msr.FE1))
GenerateProgramException(ProgramExceptionCause::FloatingPoint); GenerateProgramException(ProgramExceptionCause::FloatingPoint);
} }

18
Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
View file

@ -254,7 +254,7 @@ void Interpreter::lmw(UGeckoInstruction inst)
{ {
u32 address = Helper_Get_EA(PowerPC::ppcState, inst); u32 address = Helper_Get_EA(PowerPC::ppcState, inst);
if ((address & 0b11) != 0 || MSR.LE) if ((address & 0b11) != 0 || PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(address); GenerateAlignmentException(address);
return; return;
@ -282,7 +282,7 @@ void Interpreter::stmw(UGeckoInstruction inst)
{ {
u32 address = Helper_Get_EA(PowerPC::ppcState, inst); u32 address = Helper_Get_EA(PowerPC::ppcState, inst);
if ((address & 0b11) != 0 || MSR.LE) if ((address & 0b11) != 0 || PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(address); GenerateAlignmentException(address);
return; return;
@ -453,7 +453,7 @@ void Interpreter::dcbf(UGeckoInstruction inst)
void Interpreter::dcbi(UGeckoInstruction inst) void Interpreter::dcbi(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -678,7 +678,7 @@ void Interpreter::lswx(UGeckoInstruction inst)
{ {
u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst); u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst);
if (MSR.LE) if (PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(EA); GenerateAlignmentException(EA);
return; return;
@ -858,7 +858,7 @@ void Interpreter::lswi(UGeckoInstruction inst)
if (inst.RA != 0) if (inst.RA != 0)
EA = rGPR[inst.RA]; EA = rGPR[inst.RA];
if (MSR.LE) if (PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(EA); GenerateAlignmentException(EA);
return; return;
@ -905,7 +905,7 @@ void Interpreter::stswi(UGeckoInstruction inst)
if (inst.RA != 0) if (inst.RA != 0)
EA = rGPR[inst.RA]; EA = rGPR[inst.RA];
if (MSR.LE) if (PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(EA); GenerateAlignmentException(EA);
return; return;
@ -943,7 +943,7 @@ void Interpreter::stswx(UGeckoInstruction inst)
{ {
u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst); u32 EA = Helper_Get_EA_X(PowerPC::ppcState, inst);
if (MSR.LE) if (PowerPC::ppcState.msr.LE)
{ {
GenerateAlignmentException(EA); GenerateAlignmentException(EA);
return; return;
@ -1051,7 +1051,7 @@ void Interpreter::sync(UGeckoInstruction inst)
void Interpreter::tlbie(UGeckoInstruction inst) void Interpreter::tlbie(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -1065,7 +1065,7 @@ void Interpreter::tlbie(UGeckoInstruction inst)
void Interpreter::tlbsync(UGeckoInstruction inst) void Interpreter::tlbsync(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
} }

22
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
View file

@ -128,18 +128,18 @@ void Interpreter::mtcrf(UGeckoInstruction inst)
void Interpreter::mfmsr(UGeckoInstruction inst) void Interpreter::mfmsr(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
} }
rGPR[inst.RD] = MSR.Hex; rGPR[inst.RD] = PowerPC::ppcState.msr.Hex;
} }
void Interpreter::mfsr(UGeckoInstruction inst) void Interpreter::mfsr(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -150,7 +150,7 @@ void Interpreter::mfsr(UGeckoInstruction inst)
void Interpreter::mfsrin(UGeckoInstruction inst) void Interpreter::mfsrin(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -162,13 +162,13 @@ void Interpreter::mfsrin(UGeckoInstruction inst)
void Interpreter::mtmsr(UGeckoInstruction inst) void Interpreter::mtmsr(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
} }
MSR.Hex = rGPR[inst.RS]; PowerPC::ppcState.msr.Hex = rGPR[inst.RS];
// FE0/FE1 may have been set // FE0/FE1 may have been set
CheckFPExceptions(PowerPC::ppcState.fpscr); CheckFPExceptions(PowerPC::ppcState.fpscr);
@ -181,7 +181,7 @@ void Interpreter::mtmsr(UGeckoInstruction inst)
void Interpreter::mtsr(UGeckoInstruction inst) void Interpreter::mtsr(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -194,7 +194,7 @@ void Interpreter::mtsr(UGeckoInstruction inst)
void Interpreter::mtsrin(UGeckoInstruction inst) void Interpreter::mtsrin(UGeckoInstruction inst)
{ {
if (MSR.PR) if (PowerPC::ppcState.msr.PR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -217,8 +217,8 @@ void Interpreter::mfspr(UGeckoInstruction inst)
const u32 index = ((inst.SPR & 0x1F) << 5) + ((inst.SPR >> 5) & 0x1F); const u32 index = ((inst.SPR & 0x1F) << 5) + ((inst.SPR >> 5) & 0x1F);
// XER, LR, CTR, and timebase halves are the only ones available in user mode. // XER, LR, CTR, and timebase halves are the only ones available in user mode.
if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR && index != SPR_TL && if (PowerPC::ppcState.msr.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR &&
index != SPR_TU) index != SPR_TL && index != SPR_TU)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;
@ -288,7 +288,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F); const u32 index = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
// XER, LR, and CTR are the only ones available to be written to in user mode // XER, LR, and CTR are the only ones available to be written to in user mode
if (MSR.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR) if (PowerPC::ppcState.msr.PR && index != SPR_XER && index != SPR_LR && index != SPR_CTR)
{ {
GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction); GenerateProgramException(ProgramExceptionCause::PrivilegedInstruction);
return; return;

4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View file

@ -758,8 +758,8 @@ void Jit64::Trace()
DEBUG_LOG_FMT(DYNA_REC, DEBUG_LOG_FMT(DYNA_REC,
"JIT64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} " "JIT64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} "
"MSR: {:08x} LR: {:08x} {} {}", "MSR: {:08x} LR: {:08x} {} {}",
PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, MSR.Hex, PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex,
PowerPC::ppcState.spr[8], regs, fregs); PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs);
} }
void Jit64::Jit(u32 em_address) void Jit64::Jit(u32 em_address)

6
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
View file

@ -320,7 +320,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
FixupBranch bat_lookup_failed; FixupBranch bat_lookup_failed;
MOV(32, R(effective_address), R(addr)); MOV(32, R(effective_address), R(addr));
const u8* loop_start = GetCodePtr(); const u8* loop_start = GetCodePtr();
if (MSR.IR) if (PowerPC::ppcState.msr.IR)
{ {
// Translate effective address to physical address. // Translate effective address to physical address.
bat_lookup_failed = BATAddressLookup(addr, tmp, PowerPC::ibat_table.data()); bat_lookup_failed = BATAddressLookup(addr, tmp, PowerPC::ibat_table.data());
@ -349,7 +349,7 @@ void Jit64::dcbx(UGeckoInstruction inst)
SwitchToFarCode(); SwitchToFarCode();
SetJumpTarget(invalidate_needed); SetJumpTarget(invalidate_needed);
if (MSR.IR) if (PowerPC::ppcState.msr.IR)
SetJumpTarget(bat_lookup_failed); SetJumpTarget(bat_lookup_failed);
BitSet32 registersInUse = CallerSavedRegistersInUse(); BitSet32 registersInUse = CallerSavedRegistersInUse();
@ -422,7 +422,7 @@ void Jit64::dcbz(UGeckoInstruction inst)
end_dcbz_hack = J_CC(CC_L); end_dcbz_hack = J_CC(CC_L);
} }
bool emit_fast_path = MSR.DR && m_jit.jo.fastmem_arena; bool emit_fast_path = PowerPC::ppcState.msr.DR && m_jit.jo.fastmem_arena;
if (emit_fast_path) if (emit_fast_path)
{ {

4
Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
View file

@ -23,7 +23,7 @@ void Jit64::psq_stXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff); JITDISABLE(bJITLoadStorePairedOff);
// For performance, the AsmCommon routines assume address translation is on. // For performance, the AsmCommon routines assume address translation is on.
FALLBACK_IF(!MSR.DR); FALLBACK_IF(!PowerPC::ppcState.msr.DR);
s32 offset = inst.SIMM_12; s32 offset = inst.SIMM_12;
bool indexed = inst.OPCD == 4; bool indexed = inst.OPCD == 4;
@ -112,7 +112,7 @@ void Jit64::psq_lXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff); JITDISABLE(bJITLoadStorePairedOff);
// For performance, the AsmCommon routines assume address translation is on. // For performance, the AsmCommon routines assume address translation is on.
FALLBACK_IF(!MSR.DR); FALLBACK_IF(!PowerPC::ppcState.msr.DR);
s32 offset = inst.SIMM_12; s32 offset = inst.SIMM_12;
bool indexed = inst.OPCD == 4; bool indexed = inst.OPCD == 4;

4
Source/Core/Core/PowerPC/Jit64Common/EmuCodeBlock.cpp
View file

@ -367,7 +367,7 @@ void EmuCodeBlock::SafeLoadToReg(X64Reg reg_value, const Gen::OpArg& opAddress,
} }
FixupBranch exit; FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || MSR.DR; const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || PowerPC::ppcState.msr.DR;
const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena; const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
if (fast_check_address) if (fast_check_address)
{ {
@ -537,7 +537,7 @@ void EmuCodeBlock::SafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acces
} }
FixupBranch exit; FixupBranch exit;
const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || MSR.DR; const bool dr_set = (flags & SAFE_LOADSTORE_DR_ON) || PowerPC::ppcState.msr.DR;
const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena; const bool fast_check_address = !slowmem && dr_set && m_jit.jo.fastmem_arena;
if (fast_check_address) if (fast_check_address)
{ {

4
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
View file

@ -705,8 +705,8 @@ void JitArm64::Trace()
DEBUG_LOG_FMT(DYNA_REC, DEBUG_LOG_FMT(DYNA_REC,
"JitArm64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} " "JitArm64 PC: {:08x} SRR0: {:08x} SRR1: {:08x} FPSCR: {:08x} "
"MSR: {:08x} LR: {:08x} {} {}", "MSR: {:08x} LR: {:08x} {} {}",
PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex, MSR.Hex, PowerPC::ppcState.pc, SRR0, SRR1, PowerPC::ppcState.fpscr.Hex,
PowerPC::ppcState.spr[8], regs, fregs); PowerPC::ppcState.msr.Hex, PowerPC::ppcState.spr[8], regs, fregs);
} }
void JitArm64::Jit(u32 em_address) void JitArm64::Jit(u32 em_address)

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View file

@ -731,7 +731,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
// Translate effective address to physical address. // Translate effective address to physical address.
const u8* loop_start = GetCodePtr(); const u8* loop_start = GetCodePtr();
FixupBranch bat_lookup_failed; FixupBranch bat_lookup_failed;
if (MSR.IR) if (PowerPC::ppcState.msr.IR)
{ {
bat_lookup_failed = bat_lookup_failed =
BATAddressLookup(physical_addr, effective_addr, WA, PowerPC::ibat_table.data()); BATAddressLookup(physical_addr, effective_addr, WA, PowerPC::ibat_table.data());
@ -760,7 +760,7 @@ void JitArm64::dcbx(UGeckoInstruction inst)
SwitchToFarCode(); SwitchToFarCode();
SetJumpTarget(invalidate_needed); SetJumpTarget(invalidate_needed);
if (MSR.IR) if (PowerPC::ppcState.msr.IR)
SetJumpTarget(bat_lookup_failed); SetJumpTarget(bat_lookup_failed);
BitSet32 gprs_to_push = gpr.GetCallerSavedUsed(); BitSet32 gprs_to_push = gpr.GetCallerSavedUsed();

4
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp
View file

@ -23,7 +23,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff); JITDISABLE(bJITLoadStorePairedOff);
// If we have a fastmem arena, the asm routines assume address translation is on. // If we have a fastmem arena, the asm routines assume address translation is on.
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !MSR.DR); FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !PowerPC::ppcState.msr.DR);
// X30 is LR // X30 is LR
// X0 is the address // X0 is the address
@ -148,7 +148,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst)
JITDISABLE(bJITLoadStorePairedOff); JITDISABLE(bJITLoadStorePairedOff);
// If we have a fastmem arena, the asm routines assume address translation is on. // If we have a fastmem arena, the asm routines assume address translation is on.
FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !MSR.DR); FALLBACK_IF(!js.assumeNoPairedQuantize && jo.fastmem_arena && !PowerPC::ppcState.msr.DR);
// X30 is LR // X30 is LR
// X0 contains the scale // X0 contains the scale

3
Source/Core/Core/PowerPC/JitCommon/JitBase.cpp
View file

@ -90,7 +90,8 @@ bool JitBase::CanMergeNextInstructions(int count) const
void JitBase::UpdateMemoryAndExceptionOptions() void JitBase::UpdateMemoryAndExceptionOptions()
{ {
bool any_watchpoints = PowerPC::memchecks.HasAny(); bool any_watchpoints = PowerPC::memchecks.HasAny();
jo.fastmem = m_fastmem_enabled && jo.fastmem_arena && (MSR.DR || !any_watchpoints); jo.fastmem =
m_fastmem_enabled && jo.fastmem_arena && (PowerPC::ppcState.msr.DR || !any_watchpoints);
jo.memcheck = m_mmu_enabled || m_pause_on_panic_enabled || any_watchpoints; jo.memcheck = m_mmu_enabled || m_pause_on_panic_enabled || any_watchpoints;
jo.fp_exceptions = m_enable_float_exceptions; jo.fp_exceptions = m_enable_float_exceptions;
jo.div_by_zero_exceptions = m_enable_div_by_zero_exceptions; jo.div_by_zero_exceptions = m_enable_div_by_zero_exceptions;

7
Source/Core/Core/PowerPC/JitCommon/JitCache.cpp
View file

@ -96,7 +96,7 @@ JitBlock* JitBaseBlockCache::AllocateBlock(u32 em_address)
JitBlock& b = block_map.emplace(physical_address, JitBlock())->second; JitBlock& b = block_map.emplace(physical_address, JitBlock())->second;
b.effectiveAddress = em_address; b.effectiveAddress = em_address;
b.physicalAddress = physical_address; b.physicalAddress = physical_address;
b.msrBits = MSR.Hex & JIT_CACHE_MSR_MASK; b.msrBits = PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK;
b.linkData.clear(); b.linkData.clear();
b.fast_block_map_index = 0; b.fast_block_map_index = 0;
return &b; return &b;
@ -171,9 +171,10 @@ const u8* JitBaseBlockCache::Dispatch()
JitBlock* block = fast_block_map[FastLookupIndexForAddress(PowerPC::ppcState.pc)]; JitBlock* block = fast_block_map[FastLookupIndexForAddress(PowerPC::ppcState.pc)];
if (!block || block->effectiveAddress != PowerPC::ppcState.pc || if (!block || block->effectiveAddress != PowerPC::ppcState.pc ||
block->msrBits != (MSR.Hex & JIT_CACHE_MSR_MASK)) block->msrBits != (PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK))
{ {
block = MoveBlockIntoFastCache(PowerPC::ppcState.pc, MSR.Hex & JIT_CACHE_MSR_MASK); block = MoveBlockIntoFastCache(PowerPC::ppcState.pc,
PowerPC::ppcState.msr.Hex & JIT_CACHE_MSR_MASK);
} }
if (!block) if (!block)

6
Source/Core/Core/PowerPC/JitInterface.cpp
View file

@ -153,12 +153,14 @@ std::variant<GetHostCodeError, GetHostCodeResult> GetHostCode(u32 address)
return GetHostCodeError::NoJitActive; return GetHostCodeError::NoJitActive;
} }
JitBlock* block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address, MSR.Hex); JitBlock* block =
g_jit->GetBlockCache()->GetBlockFromStartAddress(address, PowerPC::ppcState.msr.Hex);
if (!block) if (!block)
{ {
for (int i = 0; i < 500; i++) for (int i = 0; i < 500; i++)
{ {
block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address - 4 * i, MSR.Hex); block = g_jit->GetBlockCache()->GetBlockFromStartAddress(address - 4 * i,
PowerPC::ppcState.msr.Hex);
if (block) if (block)
break; break;
} }

45
Source/Core/Core/PowerPC/MMU.cpp
View file

@ -191,7 +191,7 @@ static T ReadFromHardware(Memory::MemoryManager& memory, u32 em_address)
bool wi = false; bool wi = false;
if (!never_translate && MSR.DR) if (!never_translate && PowerPC::ppcState.msr.DR)
{ {
auto translated_addr = TranslateAddress<flag>(em_address); auto translated_addr = TranslateAddress<flag>(em_address);
if (!translated_addr.Success()) if (!translated_addr.Success())
@ -303,7 +303,7 @@ static void WriteToHardware(Core::System& system, Memory::MemoryManager& memory,
bool wi = false; bool wi = false;
if (!never_translate && MSR.DR) if (!never_translate && PowerPC::ppcState.msr.DR)
{ {
auto translated_addr = TranslateAddress<flag>(em_address); auto translated_addr = TranslateAddress<flag>(em_address);
if (!translated_addr.Success()) if (!translated_addr.Success())
@ -489,7 +489,7 @@ u32 Read_Opcode(u32 address)
TryReadInstResult TryReadInstruction(u32 address) TryReadInstResult TryReadInstruction(u32 address)
{ {
bool from_bat = true; bool from_bat = true;
if (MSR.IR) if (PowerPC::ppcState.msr.IR)
{ {
auto tlb_addr = TranslateAddress<XCheckTLBFlag::Opcode>(address); auto tlb_addr = TranslateAddress<XCheckTLBFlag::Opcode>(address);
if (!tlb_addr.Success()) if (!tlb_addr.Success())
@ -540,7 +540,7 @@ std::optional<ReadResult<u32>> HostTryReadInstruction(const u32 address,
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
{ {
const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address); const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address);
return ReadResult<u32>(!!MSR.DR, value); return ReadResult<u32>(!!PowerPC::ppcState.msr.DR, value);
} }
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
{ {
@ -550,7 +550,7 @@ std::optional<ReadResult<u32>> HostTryReadInstruction(const u32 address,
} }
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
{ {
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return std::nullopt; return std::nullopt;
const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address); const u32 value = ReadFromHardware<XCheckTLBFlag::OpcodeNoException, u32>(memory, address);
return ReadResult<u32>(true, value); return ReadResult<u32>(true, value);
@ -661,7 +661,7 @@ static std::optional<ReadResult<T>> HostTryReadUX(const u32 address, RequestedAd
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
{ {
T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address); T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address);
return ReadResult<T>(!!MSR.DR, std::move(value)); return ReadResult<T>(!!PowerPC::ppcState.msr.DR, std::move(value));
} }
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
{ {
@ -670,7 +670,7 @@ static std::optional<ReadResult<T>> HostTryReadUX(const u32 address, RequestedAd
} }
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
{ {
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return std::nullopt; return std::nullopt;
T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address); T value = ReadFromHardware<XCheckTLBFlag::NoException, T>(memory, address);
return ReadResult<T>(true, std::move(value)); return ReadResult<T>(true, std::move(value));
@ -880,12 +880,12 @@ static std::optional<WriteResult> HostTryWriteUX(const u32 var, const u32 addres
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size); WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size);
return WriteResult(!!MSR.DR); return WriteResult(!!PowerPC::ppcState.msr.DR);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
WriteToHardware<XCheckTLBFlag::NoException, true>(system, memory, address, var, size); WriteToHardware<XCheckTLBFlag::NoException, true>(system, memory, address, var, size);
return WriteResult(false); return WriteResult(false);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return std::nullopt; return std::nullopt;
WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size); WriteToHardware<XCheckTLBFlag::NoException>(system, memory, address, var, size);
return WriteResult(true); return WriteResult(true);
@ -980,7 +980,7 @@ bool IsOptimizableRAMAddress(const u32 address)
if (PowerPC::memchecks.HasAny()) if (PowerPC::memchecks.HasAny())
return false; return false;
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return false; return false;
// TODO: This API needs to take an access size // TODO: This API needs to take an access size
@ -1032,11 +1032,11 @@ bool HostIsRAMAddress(u32 address, RequestedAddressSpace space)
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, MSR.DR); return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, PowerPC::ppcState.msr.DR);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, false); return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, false);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return false; return false;
return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, true); return IsRAMAddress<XCheckTLBFlag::NoException>(memory, address, true);
} }
@ -1057,11 +1057,12 @@ bool HostIsInstructionRAMAddress(u32 address, RequestedAddressSpace space)
switch (space) switch (space)
{ {
case RequestedAddressSpace::Effective: case RequestedAddressSpace::Effective:
return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, MSR.IR); return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address,
PowerPC::ppcState.msr.IR);
case RequestedAddressSpace::Physical: case RequestedAddressSpace::Physical:
return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, false); return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, false);
case RequestedAddressSpace::Virtual: case RequestedAddressSpace::Virtual:
if (!MSR.IR) if (!PowerPC::ppcState.msr.IR)
return false; return false;
return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, true); return IsRAMAddress<XCheckTLBFlag::OpcodeNoException>(memory, address, true);
} }
@ -1151,7 +1152,7 @@ void DMA_MemoryToLC(const u32 cache_address, const u32 mem_address, const u32 nu
void ClearDCacheLine(u32 address) void ClearDCacheLine(u32 address)
{ {
DEBUG_ASSERT((address & 0x1F) == 0); DEBUG_ASSERT((address & 0x1F) == 0);
if (MSR.DR) if (PowerPC::ppcState.msr.DR)
{ {
auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address); auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT) if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@ -1183,7 +1184,7 @@ void StoreDCacheLine(u32 address)
{ {
address &= ~0x1F; address &= ~0x1F;
if (MSR.DR) if (PowerPC::ppcState.msr.DR)
{ {
auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address); auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT) if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@ -1207,7 +1208,7 @@ void InvalidateDCacheLine(u32 address)
{ {
address &= ~0x1F; address &= ~0x1F;
if (MSR.DR) if (PowerPC::ppcState.msr.DR)
{ {
auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address); auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT) if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@ -1229,7 +1230,7 @@ void FlushDCacheLine(u32 address)
{ {
address &= ~0x1F; address &= ~0x1F;
if (MSR.DR) if (PowerPC::ppcState.msr.DR)
{ {
auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address); auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT) if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@ -1253,7 +1254,7 @@ void TouchDCacheLine(u32 address, bool store)
{ {
address &= ~0x1F; address &= ~0x1F;
if (MSR.DR) if (PowerPC::ppcState.msr.DR)
{ {
auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address); auto translated_address = TranslateAddress<XCheckTLBFlag::Write>(address);
if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT) if (translated_address.result == TranslateAddressResultEnum::DIRECT_STORE_SEGMENT)
@ -1278,7 +1279,7 @@ u32 IsOptimizableMMIOAccess(u32 address, u32 access_size)
if (PowerPC::memchecks.HasAny()) if (PowerPC::memchecks.HasAny())
return 0; return 0;
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return 0; return 0;
// Translate address // Translate address
@ -1301,7 +1302,7 @@ bool IsOptimizableGatherPipeWrite(u32 address)
if (PowerPC::memchecks.HasAny()) if (PowerPC::memchecks.HasAny())
return false; return false;
if (!MSR.DR) if (!PowerPC::ppcState.msr.DR)
return false; return false;
// Translate address, only check BAT mapping. // Translate address, only check BAT mapping.
@ -1317,7 +1318,7 @@ bool IsOptimizableGatherPipeWrite(u32 address)
TranslateResult JitCache_TranslateAddress(u32 address) TranslateResult JitCache_TranslateAddress(u32 address)
{ {
if (!MSR.IR) if (!PowerPC::ppcState.msr.IR)
return TranslateResult{address}; return TranslateResult{address};
// TODO: We shouldn't use FLAG_OPCODE if the caller is the debugger. // TODO: We shouldn't use FLAG_OPCODE if the caller is the debugger.

56
Source/Core/Core/PowerPC/PowerPC.cpp
View file

@ -491,9 +491,9 @@ void CheckExceptions()
{ {
SRR0 = PowerPC::ppcState.npc; SRR0 = PowerPC::ppcState.npc;
// Page fault occurred // Page fault occurred
SRR1 = (MSR.Hex & 0x87C0FFFF) | (1 << 30); SRR1 = (PowerPC::ppcState.msr.Hex & 0x87C0FFFF) | (1 << 30);
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000400; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000400;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_ISI"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_ISI");
@ -503,9 +503,9 @@ void CheckExceptions()
{ {
SRR0 = PowerPC::ppcState.pc; SRR0 = PowerPC::ppcState.pc;
// SRR1 was partially set by GenerateProgramException, so bitwise or is used here // SRR1 was partially set by GenerateProgramException, so bitwise or is used here
SRR1 |= MSR.Hex & 0x87C0FFFF; SRR1 |= PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000700; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000700;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PROGRAM"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PROGRAM");
@ -514,9 +514,9 @@ void CheckExceptions()
else if (exceptions & EXCEPTION_SYSCALL) else if (exceptions & EXCEPTION_SYSCALL)
{ {
SRR0 = PowerPC::ppcState.npc; SRR0 = PowerPC::ppcState.npc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000C00; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000C00;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_SYSCALL (PC={:08x})", PowerPC::ppcState.pc); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_SYSCALL (PC={:08x})", PowerPC::ppcState.pc);
@ -526,9 +526,9 @@ void CheckExceptions()
{ {
// This happens a lot - GameCube OS uses deferred FPU context switching // This happens a lot - GameCube OS uses deferred FPU context switching
SRR0 = PowerPC::ppcState.pc; // re-execute the instruction SRR0 = PowerPC::ppcState.pc; // re-execute the instruction
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000800; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000800;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_FPU_UNAVAILABLE"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_FPU_UNAVAILABLE");
@ -541,9 +541,9 @@ void CheckExceptions()
else if (exceptions & EXCEPTION_DSI) else if (exceptions & EXCEPTION_DSI)
{ {
SRR0 = PowerPC::ppcState.pc; SRR0 = PowerPC::ppcState.pc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000300; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000300;
// DSISR and DAR regs are changed in GenerateDSIException() // DSISR and DAR regs are changed in GenerateDSIException()
@ -553,9 +553,9 @@ void CheckExceptions()
else if (exceptions & EXCEPTION_ALIGNMENT) else if (exceptions & EXCEPTION_ALIGNMENT)
{ {
SRR0 = PowerPC::ppcState.pc; SRR0 = PowerPC::ppcState.pc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000600; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000600;
// TODO crazy amount of DSISR options to check out // TODO crazy amount of DSISR options to check out
@ -577,15 +577,15 @@ void CheckExternalExceptions()
// EXTERNAL INTERRUPT // EXTERNAL INTERRUPT
// Handling is delayed until MSR.EE=1. // Handling is delayed until MSR.EE=1.
if (exceptions && MSR.EE) if (exceptions && PowerPC::ppcState.msr.EE)
{ {
if (exceptions & EXCEPTION_EXTERNAL_INT) if (exceptions & EXCEPTION_EXTERNAL_INT)
{ {
// Pokemon gets this "too early", it hasn't a handler yet // Pokemon gets this "too early", it hasn't a handler yet
SRR0 = PowerPC::ppcState.npc; SRR0 = PowerPC::ppcState.npc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000500; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000500;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_EXTERNAL_INT"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_EXTERNAL_INT");
@ -596,9 +596,9 @@ void CheckExternalExceptions()
else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR) else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
{ {
SRR0 = PowerPC::ppcState.npc; SRR0 = PowerPC::ppcState.npc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000F00; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000F00;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
@ -607,9 +607,9 @@ void CheckExternalExceptions()
else if (exceptions & EXCEPTION_DECREMENTER) else if (exceptions & EXCEPTION_DECREMENTER)
{ {
SRR0 = PowerPC::ppcState.npc; SRR0 = PowerPC::ppcState.npc;
SRR1 = MSR.Hex & 0x87C0FFFF; SRR1 = PowerPC::ppcState.msr.Hex & 0x87C0FFFF;
MSR.LE = MSR.ILE; PowerPC::ppcState.msr.LE = PowerPC::ppcState.msr.ILE;
MSR.Hex &= ~0x04EF36; PowerPC::ppcState.msr.Hex &= ~0x04EF36;
PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000900; PowerPC::ppcState.pc = PowerPC::ppcState.npc = 0x00000900;
DEBUG_LOG_FMT(POWERPC, "EXCEPTION_DECREMENTER"); DEBUG_LOG_FMT(POWERPC, "EXCEPTION_DECREMENTER");

1
Source/Core/Core/PowerPC/PowerPC.h
View file

@ -245,7 +245,6 @@ void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst);
#define THRM1(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM1]) #define THRM1(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM1])
#define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2]) #define THRM2(ppc_state) ((UReg_THRM12&)(ppc_state).spr[SPR_THRM2])
#define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3]) #define THRM3(ppc_state) ((UReg_THRM3&)(ppc_state).spr[SPR_THRM3])
#define MSR PowerPC::ppcState.msr
#define GPR(n) PowerPC::ppcState.gpr[n] #define GPR(n) PowerPC::ppcState.gpr[n]
#define rGPR PowerPC::ppcState.gpr #define rGPR PowerPC::ppcState.gpr