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4a9b26de86
The benefit to exposing this over the raw BP state is that adjustments Dolphin makes, such as LOD biases from arbitrary mipmap detection, will work properly.
73 lines
1.9 KiB
C++
73 lines
1.9 KiB
C++
// Copyright 2019 Dolphin Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma once
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#include <bitset>
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#include <unordered_map>
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#include "VideoBackends/D3D12/Common.h"
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#include "VideoCommon/RenderState.h"
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namespace DX12
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{
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// This class provides an abstraction for D3D12 descriptor heaps.
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struct DescriptorHandle final
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{
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D3D12_CPU_DESCRIPTOR_HANDLE cpu_handle;
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D3D12_GPU_DESCRIPTOR_HANDLE gpu_handle;
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u32 index;
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operator bool() const { return cpu_handle.ptr != 0; }
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};
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class DescriptorHeapManager final
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{
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public:
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DescriptorHeapManager();
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~DescriptorHeapManager();
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ID3D12DescriptorHeap* GetDescriptorHeap() const { return m_descriptor_heap.Get(); }
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u32 GetDescriptorIncrementSize() const { return m_descriptor_increment_size; }
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bool Create(ID3D12Device* device, D3D12_DESCRIPTOR_HEAP_TYPE type, u32 num_descriptors);
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bool Allocate(DescriptorHandle* handle);
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void Free(const DescriptorHandle& handle);
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void Free(u32 index);
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private:
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ComPtr<ID3D12DescriptorHeap> m_descriptor_heap;
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u32 m_num_descriptors = 0;
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u32 m_descriptor_increment_size = 0;
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D3D12_CPU_DESCRIPTOR_HANDLE m_heap_base_cpu = {};
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D3D12_GPU_DESCRIPTOR_HANDLE m_heap_base_gpu = {};
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static constexpr u32 BITSET_SIZE = 1024;
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using BitSetType = std::bitset<BITSET_SIZE>;
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std::vector<BitSetType> m_free_slots = {};
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};
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class SamplerHeapManager final
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{
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public:
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SamplerHeapManager();
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~SamplerHeapManager();
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ID3D12DescriptorHeap* GetDescriptorHeap() const { return m_descriptor_heap.Get(); }
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bool Create(ID3D12Device* device, u32 num_descriptors);
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bool Lookup(const SamplerState& ss, D3D12_CPU_DESCRIPTOR_HANDLE* handle);
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void Clear();
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private:
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ComPtr<ID3D12DescriptorHeap> m_descriptor_heap;
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u32 m_num_descriptors = 0;
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u32 m_descriptor_increment_size = 0;
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u32 m_current_offset = 0;
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D3D12_CPU_DESCRIPTOR_HANDLE m_heap_base_cpu{};
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std::unordered_map<SamplerState, D3D12_CPU_DESCRIPTOR_HANDLE> m_sampler_map;
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};
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} // namespace DX12
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